diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-08-23 19:11:14 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2006-08-23 19:11:14 +0000 |
commit | 83fb86f32b73942be758c22423c0bfe506fd4ff6 (patch) | |
tree | d51a136781eaccf67bfb2addfbe5330d9aed4791 /doc/supplements/sparc/bsp.t | |
parent | 2006-08-23 Joel Sherrill <joel@OARcorp.com> (diff) | |
download | rtems-83fb86f32b73942be758c22423c0bfe506fd4ff6.tar.bz2 |
2006-08-23 Joel Sherrill <joel@OARcorp.com>
* Makefile.am, configure.ac, FAQ/stamp-vti, FAQ/version.texi,
common/cpright.texi: Merging CPU Supplements into a single document.
As part of this removed the obsolete and impossible to maintain size
and timing information.
* cpu_supplement/.cvsignore, cpu_supplement/Makefile.am,
cpu_supplement/arm.t, cpu_supplement/i386.t, cpu_supplement/m68k.t,
cpu_supplement/mips.t, cpu_supplement/powerpc.t,
cpu_supplement/preface.texi, cpu_supplement/sh.t,
cpu_supplement/sparc.t, cpu_supplement/tic4x.t: New files.
* supplements/.cvsignore, supplements/Makefile.am,
supplements/supplement.am, supplements/arm/.cvsignore,
supplements/arm/BSP_TIMES, supplements/arm/ChangeLog,
supplements/arm/Makefile.am, supplements/arm/arm.texi,
supplements/arm/bsp.t, supplements/arm/callconv.t,
supplements/arm/cpumodel.t, supplements/arm/cputable.t,
supplements/arm/fatalerr.t, supplements/arm/intr_NOTIMES.t,
supplements/arm/memmodel.t, supplements/arm/preface.texi,
supplements/arm/timeBSP.t, supplements/c4x/.cvsignore,
supplements/c4x/BSP_TIMES, supplements/c4x/ChangeLog,
supplements/c4x/Makefile.am, supplements/c4x/bsp.t,
supplements/c4x/c4x.texi, supplements/c4x/callconv.t,
supplements/c4x/cpumodel.t, supplements/c4x/cputable.t,
supplements/c4x/fatalerr.t, supplements/c4x/intr_NOTIMES.t,
supplements/c4x/memmodel.t, supplements/c4x/preface.texi,
supplements/c4x/timeBSP.t, supplements/i386/.cvsignore,
supplements/i386/ChangeLog, supplements/i386/FORCE386_TIMES,
supplements/i386/Makefile.am, supplements/i386/bsp.t,
supplements/i386/callconv.t, supplements/i386/cpumodel.t,
supplements/i386/cputable.t, supplements/i386/fatalerr.t,
supplements/i386/i386.texi, supplements/i386/intr_NOTIMES.t,
supplements/i386/memmodel.t, supplements/i386/preface.texi,
supplements/i386/timeFORCE386.t, supplements/m68k/.cvsignore,
supplements/m68k/ChangeLog, supplements/m68k/MVME136_TIMES,
supplements/m68k/Makefile.am, supplements/m68k/bsp.t,
supplements/m68k/callconv.t, supplements/m68k/cpumodel.t,
supplements/m68k/cputable.t, supplements/m68k/fatalerr.t,
supplements/m68k/intr_NOTIMES.t, supplements/m68k/m68k.texi,
supplements/m68k/memmodel.t, supplements/m68k/preface.texi,
supplements/m68k/timeMVME136.t, supplements/m68k/timedata.t,
supplements/mips/.cvsignore, supplements/mips/BSP_TIMES,
supplements/mips/ChangeLog, supplements/mips/Makefile.am,
supplements/mips/bsp.t, supplements/mips/callconv.t,
supplements/mips/cpumodel.t, supplements/mips/cputable.t,
supplements/mips/fatalerr.t, supplements/mips/intr_NOTIMES.t,
supplements/mips/memmodel.t, supplements/mips/mips.texi,
supplements/mips/preface.texi, supplements/mips/timeBSP.t,
supplements/powerpc/.cvsignore, supplements/powerpc/ChangeLog,
supplements/powerpc/DMV177_TIMES, supplements/powerpc/Makefile.am,
supplements/powerpc/PSIM_TIMES, supplements/powerpc/bsp.t,
supplements/powerpc/callconv.t, supplements/powerpc/cpumodel.t,
supplements/powerpc/cputable.t, supplements/powerpc/fatalerr.t,
supplements/powerpc/intr_NOTIMES.t, supplements/powerpc/memmodel.t,
supplements/powerpc/powerpc.texi, supplements/powerpc/preface.texi,
supplements/powerpc/timeDMV177.t, supplements/powerpc/timePSIM.t,
supplements/sh/.cvsignore, supplements/sh/BSP_TIMES,
supplements/sh/ChangeLog, supplements/sh/Makefile.am,
supplements/sh/bsp.t, supplements/sh/callconv.t,
supplements/sh/cpumodel.t, supplements/sh/cputable.t,
supplements/sh/fatalerr.t, supplements/sh/intr_NOTIMES.t,
supplements/sh/memmodel.t, supplements/sh/preface.texi,
supplements/sh/sh.texi, supplements/sh/timeBSP.t,
supplements/sparc/.cvsignore, supplements/sparc/ChangeLog,
supplements/sparc/ERC32_TIMES, supplements/sparc/Makefile.am,
supplements/sparc/bsp.t, supplements/sparc/callconv.t,
supplements/sparc/cpumodel.t, supplements/sparc/cputable.t,
supplements/sparc/fatalerr.t, supplements/sparc/intr_NOTIMES.t,
supplements/sparc/memmodel.t, supplements/sparc/preface.texi,
supplements/sparc/sparc.texi, supplements/sparc/timeERC32.t,
supplements/template/.cvsignore, supplements/template/BSP_TIMES,
supplements/template/ChangeLog, supplements/template/Makefile.am,
supplements/template/bsp.t, supplements/template/callconv.t,
supplements/template/cpumodel.t, supplements/template/cputable.t,
supplements/template/fatalerr.t, supplements/template/intr_NOTIMES.t,
supplements/template/memmodel.t, supplements/template/preface.texi,
supplements/template/template.texi, supplements/template/timeBSP.t: Removed.
Diffstat (limited to 'doc/supplements/sparc/bsp.t')
-rw-r--r-- | doc/supplements/sparc/bsp.t | 87 |
1 files changed, 0 insertions, 87 deletions
diff --git a/doc/supplements/sparc/bsp.t b/doc/supplements/sparc/bsp.t deleted file mode 100644 index 8810614825..0000000000 --- a/doc/supplements/sparc/bsp.t +++ /dev/null @@ -1,87 +0,0 @@ -@c -@c COPYRIGHT (c) 1988-2002. -@c On-Line Applications Research Corporation (OAR). -@c All rights reserved. -@c -@c $Id$ -@c - -@chapter Board Support Packages - -@section Introduction - -An RTEMS Board Support Package (BSP) must be designed -to support a particular processor and target board combination. -This chapter presents a discussion of SPARC specific BSP issues. -For more information on developing a BSP, refer to the chapter -titled Board Support Packages in the RTEMS -Applications User's Guide. - -@section System Reset - -An RTEMS based application is initiated or -re-initiated when the SPARC processor is reset. When the SPARC -is reset, the processor performs the following actions: - -@itemize @bullet -@item the enable trap (ET) of the psr is set to 0 to disable -traps, - -@item the supervisor bit (S) of the psr is set to 1 to enter -supervisor mode, and - -@item the PC is set 0 and the nPC is set to 4. -@end itemize - -The processor then begins to execute the code at -location 0. It is important to note that all fields in the psr -are not explicitly set by the above steps and all other -registers retain their value from the previous execution mode. -This is true even of the Trap Base Register (TBR) whose contents -reflect the last trap which occurred before the reset. - -@section Processor Initialization - -It is the responsibility of the application's -initialization code to initialize the TBR and install trap -handlers for at least the register window overflow and register -window underflow conditions. Traps should be enabled before -invoking any subroutines to allow for register window -management. However, interrupts should be disabled by setting -the Processor Interrupt Level (pil) field of the psr to 15. -RTEMS installs it's own Trap Table as part of initialization -which is initialized with the contents of the Trap Table in -place when the @code{rtems_initialize_executive} directive was invoked. -Upon completion of executive initialization, interrupts are -enabled. - -If this SPARC implementation supports on-chip caching -and this is to be utilized, then it should be enabled during the -reset application initialization code. - -In addition to the requirements described in the -Board Support Packages chapter of the @value{LANGUAGE} -Applications User's Manual for the reset code -which is executed before the call to -@code{rtems_initialize_executive}, the SPARC version has the following -specific requirements: - -@itemize @bullet -@item Must leave the S bit of the status register set so that -the SPARC remains in the supervisor state. - -@item Must set stack pointer (sp) such that a minimum stack -size of MINIMUM_STACK_SIZE bytes is provided for the -@code{rtems_initialize_executive} directive. - -@item Must disable all external interrupts (i.e. set the pil -to 15). - -@item Must enable traps so window overflow and underflow -conditions can be properly handled. - -@item Must initialize the SPARC's initial trap table with at -least trap handlers for register window overflow and register -window underflow. -@end itemize - |