minor updates .. mostly version

1 files changed, 22 insertions, 21 deletions

diff --git a/doc/supplements/powerpc/callconv.t b/doc/supplements/powerpc/callconv.t
index cf71e47d26..dd7b0b00c2 100644
--- a/doc/supplements/powerpc/callconv.t
+++ b/doc/supplements/powerpc/callconv.t
@@ -153,25 +153,17 @@ The following table describes the role of each of these registers:
 @end ifinfo
 @subsection Floating Point Registers
 
-The SPARC V7 architecture includes thirty-two,
-thirty-two bit registers.  These registers may be viewed as
-follows:
+The PowerPC architecture includes thirty-two,
+sixty-four bit registers.  All PowwerPC floating point instructions 
+interprete these registers as 32 double precision floating point registers,
+regardless of whether the processor has 64-bit or 32-bit implementation.
 
-@itemize @bullet
-@item 32 single precision floating point or integer registers
-(f0, f1,  ... f31)
-
-@item 16 double precision floating point registers (f0, f2,
-f4, ... f30)
-
-@item 8 extended precision floating point registers (f0, f4,
-f8, ... f28)
-@end itemize
-
-The floating point status register (fpsr) specifies
-the behavior of the floating point unit for rounding, contains
-its condition codes, version specification, and trap information.
+The floating point status and control register (fpscr) records exceptions
+and the type of result generated by floating-point operations.
+Additionally, it controls the rounding mode of operations and allows the
+reporting of floating exceptions to be enabled or disabled.
 
+XXXXXX
 A queue of the floating point instructions which have
 started execution but not yet completed is maintained.  This
 queue is needed to support the multiple cycle nature of floating
@@ -183,22 +175,29 @@ It is emptied normally when the floating point completes all
 outstanding instructions and by floating point exception
 handlers with the store double floating point queue (stdfq)
 instruction.
+XXX
 
 @ifinfo
 @node Special Registers, Calling Conventions Register Windows, Floating Point Registers, Calling Conventions Programming Model
 @end ifinfo
 @subsection Special Registers
 
-The SPARC architecture includes two special registers
-which are critical to the programming model: the Processor State
-Register (psr) and the Window Invalid Mask (wim).  The psr
-contains the condition codes, processor interrupt level, trap
+The PowerPC architecture includes XXX special registers
+which are critical to the programming model: the Machine State
+Register (msr) and XXX the Window Invalid Mask (wim) XXX.  The msr
+contains the processor mode, power management mode, endian mode, exception
+information, privlige level, floating point available and floating point 
+excepiton mode, address translation information and the exception prefix.
+
+XXX
+condition codes, processor interrupt level, trap
 enable bit, supervisor mode and previous supervisor mode bits,
 version information, floating point unit and coprocessor enable
 bits, and the current window pointer (cwp).  The cwp field of
 the psr and wim register are used to manage the register windows
 in the SPARC architecture.  The register windows are discussed
 in more detail below.
+XXX
 
 @ifinfo
 @node Calling Conventions Register Windows, Calling Conventions Call and Return Mechanism, Special Registers, Calling Conventions
@@ -369,3 +368,5 @@ All user-provided routines invoked by RTEMS, such as
 user extensions, device drivers, and MPCI routines, must also
 adhere to these calling conventions.
 
+
+