updates

1 files changed, 32 insertions, 44 deletions

diff --git a/doc/supplements/powerpc/bsp.t b/doc/supplements/powerpc/bsp.t
index 99fdd3fb94..015f7347e0 100644
--- a/doc/supplements/powerpc/bsp.t
+++ b/doc/supplements/powerpc/bsp.t
@@ -36,26 +36,17 @@ Applications User's Guide.
 @section System Reset
 
 An RTEMS based application is initiated or
-re-initiated when the PowerPC processor is reset.  When the PowerPC
-is reset, the processor performs the following actions:
-
-@itemize @bullet
-@item TBD
-
-@item TBD
-
-@item TBD
-@end itemize
-
-The processor then begins to execute the code at location 0x00100.  
-By using the SRR1 bit corresponding to MSR[RI] the softwere may 
-distinguish between power-on reset and other types of system resets.
-
-It is important to note that all fields in the psr
-are not explicitly set by the above steps and all other
-registers retain their value from the previous execution mode.
-This is true even of the Trap Base Register (TBR) whose contents
-reflect the last trap which occurred before the reset.
+re-initiated when the PowerPC processor is reset.  The PowerPC 
+architecture defines a Reset Exception, but leaves the
+details of the CPU state as implementation specific.  Please
+refer to the User's Manual for the CPU model in question.
+
+In general, at power-up the PowerPC begin execution at address
+0xFFF00100 in supervisor mode with all exceptions disabled.  For
+soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100
+depending upon the setting of the Exception Prefix bit in the MSR.
+If during a soft reset, a Machine Check Exception occurs, then the
+CPU may execute a hard reset.
 
 @ifinfo
 @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
@@ -63,36 +54,33 @@ reflect the last trap which occurred before the reset.
 @section Processor Initialization
 
 It is the responsibility of the application's
-initialization code to initialize the TBR and install trap
-handlers for at least the register window overflow and register
-window underflow conditions.  Traps should be enabled before
-invoking any subroutines to allow for register window
-management.  However, interrupts should be disabled by setting
-the Processor Interrupt Level (pil) field of the psr to 15.
-RTEMS installs it's own Trap Table as part of initialization
-which is initialized with the contents of the Trap Table in
-place when the rtems_initialize_executive directive was invoked.
-Upon completion of executive initialization, interrupts are
-enabled.
+initialization code to initialize the CPU and board
+to a quiescent state before invoking the @code{rtems_initialize_executive}
+directive.  It is recommended that the BSP utilize the @code{predriver_hook}
+to install default handlers for all exceptions.  These default handlers
+may be overwritten as various device drivers and subsystems install
+their own exception handlers.  Upon completion of RTEMS executive
+initialization, all interrupts are enabled.
 
 If this PowerPC implementation supports on-chip caching
 and this is to be utilized, then it should be enabled during the
-reset application initialization code.
+reset application initialization code.  On-chip caching has been
+observed to prevent some emulators from working properly, so it
+may be necessary to run with caching disabled to use these emulators.
 
 In addition to the requirements described in the
-Board Support Packages chapter of the @value{LANGUAGE}
-Applications User's Manual for the reset code
-which is executed before the call to
-rtems_initialize executive, the PowrePC version has the following
-specific requirements:
+@b{Board Support Packages} chapter of the @b{@value{LANGUAGE}
+Applications User's Manual} for the reset code
+which is executed before the call to @code{rtems_initialize_executive},
+the PowrePC version has the following specific requirements:
 
 @itemize @bullet
-@item Must leave the PR bit of the machine state register set so that
-the PowerPC remains in the supervisor state.
+@item Must leave the PR bit of the Machine State Register (MSR) set 
+to 0 so the PowerPC remains in the supervisor state.
 
-@item Must set stack pointer (sp) such that a minimum stack
+@item Must set stack pointer (sp or r1) such that a minimum stack
 size of MINIMUM_STACK_SIZE bytes is provided for the
-rtems_initialize executive directive.
+@code{rtems_initialize_executive} directive.
 
 @item Must disable all external interrupts (i.e. clear the EI (EE)
 bit of the machine state register).
@@ -100,8 +88,8 @@ bit of the machine state register).
 @item Must enable traps so window overflow and underflow
 conditions can be properly handled.
 
-@item Must initialize the PowerPC's initial trap table with at
-least trap handlers for register window overflow and register
-window underflow.
+@item Must initialize the PowerPC's initial Exception Table with default
+handlers.
+
 @end itemize