2006-08-23 Joel Sherrill <joel@OARcorp.com>

	* Makefile.am, configure.ac, FAQ/stamp-vti, FAQ/version.texi,
	common/cpright.texi: Merging CPU Supplements into a single document.
	As part of this removed the obsolete and impossible to maintain size
	and timing information.
	* cpu_supplement/.cvsignore, cpu_supplement/Makefile.am,
	cpu_supplement/arm.t, cpu_supplement/i386.t, cpu_supplement/m68k.t,
	cpu_supplement/mips.t, cpu_supplement/powerpc.t,
	cpu_supplement/preface.texi, cpu_supplement/sh.t,
	cpu_supplement/sparc.t, cpu_supplement/tic4x.t: New files.
	* supplements/.cvsignore, supplements/Makefile.am,
	supplements/supplement.am, supplements/arm/.cvsignore,
	supplements/arm/BSP_TIMES, supplements/arm/ChangeLog,
	supplements/arm/Makefile.am, supplements/arm/arm.texi,
	supplements/arm/bsp.t, supplements/arm/callconv.t,
	supplements/arm/cpumodel.t, supplements/arm/cputable.t,
	supplements/arm/fatalerr.t, supplements/arm/intr_NOTIMES.t,
	supplements/arm/memmodel.t, supplements/arm/preface.texi,
	supplements/arm/timeBSP.t, supplements/c4x/.cvsignore,
	supplements/c4x/BSP_TIMES, supplements/c4x/ChangeLog,
	supplements/c4x/Makefile.am, supplements/c4x/bsp.t,
	supplements/c4x/c4x.texi, supplements/c4x/callconv.t,
	supplements/c4x/cpumodel.t, supplements/c4x/cputable.t,
	supplements/c4x/fatalerr.t, supplements/c4x/intr_NOTIMES.t,
	supplements/c4x/memmodel.t, supplements/c4x/preface.texi,
	supplements/c4x/timeBSP.t, supplements/i386/.cvsignore,
	supplements/i386/ChangeLog, supplements/i386/FORCE386_TIMES,
	supplements/i386/Makefile.am, supplements/i386/bsp.t,
	supplements/i386/callconv.t, supplements/i386/cpumodel.t,
	supplements/i386/cputable.t, supplements/i386/fatalerr.t,
	supplements/i386/i386.texi, supplements/i386/intr_NOTIMES.t,
	supplements/i386/memmodel.t, supplements/i386/preface.texi,
	supplements/i386/timeFORCE386.t, supplements/m68k/.cvsignore,
	supplements/m68k/ChangeLog, supplements/m68k/MVME136_TIMES,
	supplements/m68k/Makefile.am, supplements/m68k/bsp.t,
	supplements/m68k/callconv.t, supplements/m68k/cpumodel.t,
	supplements/m68k/cputable.t, supplements/m68k/fatalerr.t,
	supplements/m68k/intr_NOTIMES.t, supplements/m68k/m68k.texi,
	supplements/m68k/memmodel.t, supplements/m68k/preface.texi,
	supplements/m68k/timeMVME136.t, supplements/m68k/timedata.t,
	supplements/mips/.cvsignore, supplements/mips/BSP_TIMES,
	supplements/mips/ChangeLog, supplements/mips/Makefile.am,
	supplements/mips/bsp.t, supplements/mips/callconv.t,
	supplements/mips/cpumodel.t, supplements/mips/cputable.t,
	supplements/mips/fatalerr.t, supplements/mips/intr_NOTIMES.t,
	supplements/mips/memmodel.t, supplements/mips/mips.texi,
	supplements/mips/preface.texi, supplements/mips/timeBSP.t,
	supplements/powerpc/.cvsignore, supplements/powerpc/ChangeLog,
	supplements/powerpc/DMV177_TIMES, supplements/powerpc/Makefile.am,
	supplements/powerpc/PSIM_TIMES, supplements/powerpc/bsp.t,
	supplements/powerpc/callconv.t, supplements/powerpc/cpumodel.t,
	supplements/powerpc/cputable.t, supplements/powerpc/fatalerr.t,
	supplements/powerpc/intr_NOTIMES.t, supplements/powerpc/memmodel.t,
	supplements/powerpc/powerpc.texi, supplements/powerpc/preface.texi,
	supplements/powerpc/timeDMV177.t, supplements/powerpc/timePSIM.t,
	supplements/sh/.cvsignore, supplements/sh/BSP_TIMES,
	supplements/sh/ChangeLog, supplements/sh/Makefile.am,
	supplements/sh/bsp.t, supplements/sh/callconv.t,
	supplements/sh/cpumodel.t, supplements/sh/cputable.t,
	supplements/sh/fatalerr.t, supplements/sh/intr_NOTIMES.t,
	supplements/sh/memmodel.t, supplements/sh/preface.texi,
	supplements/sh/sh.texi, supplements/sh/timeBSP.t,
	supplements/sparc/.cvsignore, supplements/sparc/ChangeLog,
	supplements/sparc/ERC32_TIMES, supplements/sparc/Makefile.am,
	supplements/sparc/bsp.t, supplements/sparc/callconv.t,
	supplements/sparc/cpumodel.t, supplements/sparc/cputable.t,
	supplements/sparc/fatalerr.t, supplements/sparc/intr_NOTIMES.t,
	supplements/sparc/memmodel.t, supplements/sparc/preface.texi,
	supplements/sparc/sparc.texi, supplements/sparc/timeERC32.t,
	supplements/template/.cvsignore, supplements/template/BSP_TIMES,
	supplements/template/ChangeLog, supplements/template/Makefile.am,
	supplements/template/bsp.t, supplements/template/callconv.t,
	supplements/template/cpumodel.t, supplements/template/cputable.t,
	supplements/template/fatalerr.t, supplements/template/intr_NOTIMES.t,
	supplements/template/memmodel.t, supplements/template/preface.texi,
	supplements/template/template.texi, supplements/template/timeBSP.t: Removed.

1 files changed, 0 insertions, 109 deletions

diff --git a/doc/supplements/i386/bsp.t b/doc/supplements/i386/bsp.t
deleted file mode 100644
index 9ac99901f1..0000000000
--- a/doc/supplements/i386/bsp.t
+++ /dev/null
@@ -1,109 +0,0 @@
-@c
-@c  COPYRIGHT (c) 1988-2002.
-@c  On-Line Applications Research Corporation (OAR).
-@c  All rights reserved.
-@c
-@c  $Id$
-@c
-
-@chapter Board Support Packages
-
-@section Introduction
-
-An RTEMS Board Support Package (BSP) must be designed to support a
-particular processor and target board combination.  This chapter presents a
-discussion of i386 specific BSP issues.  For more information on developing
-a BSP, refer to the chapter titled Board Support Packages in the RTEMS
-Applications User's Guide. 
-
-@section System Reset
-
-An RTEMS based application is initiated when the i386
-processor is reset.  When the i386 is reset,
-
-@itemize @bullet
-
-@item The EAX register is set to indicate the results of the processor's
-power-up self test.  If the self-test was not executed, the contents of
-this register are undefined.  Otherwise, a non-zero value indicates the
-processor is faulty and a zero value indicates a successful self-test.
-
-@item The DX register holds a component identifier and revision level.  DH
-contains 3 to indicate an i386 component and DL contains a unique revision
-level indicator. 
-
-@item Control register zero (CR0) is set such that the processor is in real
-mode with paging disabled.  Other portions of CR0 are used to indicate the
-presence of a numeric coprocessor. 
-
-@item All bits in the extended flags register (EFLAG) which are not
-permanently set are cleared.  This inhibits all maskable interrupts. 
-
-@item The Interrupt Descriptor Register (IDTR) is set to point at address
-zero. 
-
-@item All segment registers are set to zero. 
-
-@item The instruction pointer is set to 0x0000FFF0.  The first instruction
-executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts
-the upper twelve address until the first intersegment (FAR) JMP or CALL
-instruction.  When a JMP or CALL is executed, the upper twelve address
-lines are lowered and the processor begins executing in the first megabyte
-of memory.
-
-@end itemize
-
-Typically, an intersegment JMP to the application's initialization code is
-placed at address 0xFFFFFFF0. 
-
-@section Processor Initialization
-
-This initialization code is responsible for initializing all data
-structures required by the i386 in protected mode and for actually entering
-protected mode.  The i386 must be placed in protected mode and the segment
-registers and associated selectors must be initialized before the
-initialize_executive directive is invoked. 
-
-The initialization code is responsible for initializing the Global
-Descriptor Table such that the i386 is in the thirty-two bit flat memory
-model with paging disabled.  In this mode, the i386 automatically converts
-every address from a logical to a physical address each time it is used. 
-For more information on the memory model used by RTEMS, please refer to the
-Memory Model chapter in this document. 
-
-Since the processor is in real mode upon reset, the processor must be
-switched to protected mode before RTEMS can execute.  Before switching to
-protected mode, at least one descriptor table and two descriptors must be
-created.  Descriptors are needed for a code segment and a data segment. (
-This will give you the flat memory model.)  The stack can be placed in a
-normal read/write data segment, so no descriptor for the stack is needed.
-Before the GDT can be used, the base address and limit must be loaded into
-the GDTR register using an LGDT instruction. 
-
-If the hardware allows an NMI to be generated, you need to create the IDT
-and a gate for the NMI interrupt handler.  Before the IDT can be used, the
-base address and limit for the idt must be loaded into the IDTR register
-using an LIDT instruction. 
-
-Protected mode is entered by setting thye PE bit in the CR0 register. 
-Either a LMSW or MOV CR0 instruction may be used to set this bit. Because
-the processor overlaps the interpretation of several instructions, it is
-necessary to discard the instructions from the read-ahead cache. A JMP
-instruction immediately after the LMSW changes the flow and empties the
-processor if intructions which have been pre-fetched and/or decoded.  At
-this point, the processor is in protected mode and begins to perform
-protected mode application initialization.
-
-If the application requires that the IDTR be some value besides zero, then
-it should set it to the required value at this point.  All tasks share the
-same i386 IDTR value.  Because interrupts are enabled automatically by
-RTEMS as part of the initialize_executive directive, the IDTR MUST be set
-properly before this directive is invoked to insure correct interrupt
-vectoring.  If processor caching is to be utilized, then it should be
-enabled during the reset application initialization code.  The reset code
-which is executed before the call to initialize_executive has the following
-requirements:
-
-For more information regarding the i386s data structures and their
-contents, refer to Intel's 386 Programmer's Reference Manual.
-