path: root/doc/porting
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authorSebastian Huber <>2013-05-07 10:14:55 +0200
committerSebastian Huber <>2013-05-10 12:10:14 +0200
commit39993d6d7693b9fd26d729efd199cc605cd2ae65 (patch)
treed06b29ef4cd1d68223c25e9de9069b445bf4aed1 /doc/porting
parentaedeb57783e4f3099ef006b1197d631308de1693 (diff)
score: Add CPU context validation
Diffstat (limited to 'doc/porting')
1 files changed, 25 insertions, 0 deletions
diff --git a/doc/porting/miscellaneous.t b/doc/porting/miscellaneous.t
index e93d5e688b..cba85f7963 100644
--- a/doc/porting/miscellaneous.t
+++ b/doc/porting/miscellaneous.t
@@ -18,6 +18,31 @@ void _CPU_Fatal_halt(
@end example
+@section CPU Context Validation
+The test case @code{sptests/spcontext01} ensures that the context switching and
+interrupt processing works. This test uses two support functions provided by
+the CPU port. These two functions are only used for this test and have no
+other purpose.
+void _CPU_Context_volatile_clobber( uintptr_t pattern );
+void _CPU_Context_validate( uintptr_t pattern );
+@end example
+The @code{_CPU_Context_volatile_clobber()} function clobbers all volatile
+registers with values derived from the pattern parameter. This makes sure that
+the interrupt prologue code restores all volatile registers of the interrupted
+The @code{_CPU_Context_validate()} function initializes and validates the CPU
+context with values derived from the pattern parameter. This function will not
+return if the CPU context remains consistent. In case this function returns
+the CPU port is broken. The test uses two threads which concurrently validate
+the CPU context with a different patterns for each thread. This ensures that
+the context switching code works.
@section Processor Endianness
Endianness refers to the order in which numeric values are stored in