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author | Daniel Cederman <cederman@gaisler.com> | 2015-01-12 11:24:16 +0100 |
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committer | Daniel Hellstrom <daniel@gaisler.com> | 2015-02-11 15:35:27 +0100 |
commit | b92f737c245eb7ba41b8d13663cd4f0845e12ea6 (patch) | |
tree | a24a5f05e26c8ea49d596a51c8f947cbdd0c1e35 /doc/cpu_supplement | |
parent | smpcapture02: Add test of functionality to add custom entries to capture trace (diff) | |
download | rtems-b92f737c245eb7ba41b8d13663cd4f0845e12ea6.tar.bz2 |
doc: Describe new default error handler for Sparc
Diffstat (limited to 'doc/cpu_supplement')
-rw-r--r-- | doc/cpu_supplement/sparc.t | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t index cd5602c2db..d21e9feef1 100644 --- a/doc/cpu_supplement/sparc.t +++ b/doc/cpu_supplement/sparc.t @@ -951,10 +951,18 @@ handler. The default fatal error handler which is invoked by the fatal_error_occurred directive when there is no user handler -configured or the user handler returns control to RTEMS. The -default fatal error handler disables processor interrupts to -level 15, places the error code in g1, and goes into an infinite -loop to simulate a halt processor instruction. +configured or the user handler returns control to RTEMS. + +If the BSP has been configured with @code{BSP_POWER_DOWN_AT_FATAL_HALT} +set to true, the default handler will disable interrupts +and enter power down mode. If power down mode is not available, +it goes into an infinite loop to simulate a halt processor instruction. + +If @code{BSP_POWER_DOWN_AT_FATAL_HALT} is set to false, the default +handler will place the value @code{1} in register @code{g1}, the +error source in register @code{g2}, and the error code in register +@code{g3}. It will then generate a system error which will +hand over control to the debugger, simulator, etc. @section Thread-Local Storage |