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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-07-23 08:36:30 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-07-23 09:12:35 +0200 |
| commit | f9a597950b1d61c9c1283dc85ae2a4c579d96263 (patch) | |
| tree | 1db8bf1a057132a196b47b6263c9fea475fe16eb /doc/cpu_supplement/mips.t | |
| parent | bsps/arm: Update due to API changes (diff) | |
| download | rtems-f9a597950b1d61c9c1283dc85ae2a4c579d96263.tar.bz2 | |
doc: Add SMP section to CPU Arch Supplement
Diffstat (limited to 'doc/cpu_supplement/mips.t')
| -rw-r--r-- | doc/cpu_supplement/mips.t | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/cpu_supplement/mips.t b/doc/cpu_supplement/mips.t index 7d6fcb3527..c966bf5e9c 100644 --- a/doc/cpu_supplement/mips.t +++ b/doc/cpu_supplement/mips.t @@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables processor interrupts, places the error code in @b{XXX}, and executes a @code{XXX} instruction to simulate a halt processor instruction. +@section Symmetric Multiprocessing + +SMP is not supported. + @section Thread-Local Storage Thread-local storage is not implemented. |