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authorSebastian Huber <sebastian.huber@embedded-brains.de>2015-07-23 08:36:30 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2015-07-23 08:36:30 +0200
commit19078dc6e60010002498e455d2b6a39fd9160ba4 (patch)
tree62d9f2ac76a9fd0584e2b4b544639525803b8969 /doc/cpu_supplement/mips.t
parentscore: Move wait flag update to tq extract (diff)
downloadrtems-19078dc6e60010002498e455d2b6a39fd9160ba4.tar.bz2
doc: Add SMP section to CPU Arch Supplement
Diffstat (limited to 'doc/cpu_supplement/mips.t')
-rw-r--r--doc/cpu_supplement/mips.t4
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/cpu_supplement/mips.t b/doc/cpu_supplement/mips.t
index 7d6fcb3527..c966bf5e9c 100644
--- a/doc/cpu_supplement/mips.t
+++ b/doc/cpu_supplement/mips.t
@@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables
processor interrupts, places the error code in @b{XXX}, and executes a
@code{XXX} instruction to simulate a halt processor instruction.
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
@section Thread-Local Storage
Thread-local storage is not implemented.