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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-01-28 12:10:08 +0100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-04 10:06:35 +0100 |
commit | 022851aba54d32831feaff13deb3d9943e130eee (patch) | |
tree | c1d6a8404dae393bd147790f6a9cf09c2f327b5a /doc/cpu_supplement/mips.t | |
parent | bsps: Thread-local storage (TLS) for linkcmds (diff) | |
download | rtems-022851aba54d32831feaff13deb3d9943e130eee.tar.bz2 |
Add thread-local storage (TLS) support
Tested and implemented on ARM, m68k, PowerPC and SPARC. Other
architectures need more work.
Diffstat (limited to 'doc/cpu_supplement/mips.t')
-rw-r--r-- | doc/cpu_supplement/mips.t | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/cpu_supplement/mips.t b/doc/cpu_supplement/mips.t index 816c43aa0d..7d6fcb3527 100644 --- a/doc/cpu_supplement/mips.t +++ b/doc/cpu_supplement/mips.t @@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables processor interrupts, places the error code in @b{XXX}, and executes a @code{XXX} instruction to simulate a halt processor instruction. +@section Thread-Local Storage + +Thread-local storage is not implemented. + @c @c @c |