2004-04-12 David Querbach <querbach@realtime.bc.ca>

	* asm.h, rtems/new-exceptions/cpu.h, rtems/score/ppc.h: addition of
	MPC555 support as part of the addition of the SS555 BSP.

5 files changed, 31 insertions, 1 deletions

diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog
index ec62d98e5e..daada29130 100644
--- a/cpukit/score/cpu/powerpc/ChangeLog
+++ b/cpukit/score/cpu/powerpc/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-12	David Querbach <querbach@realtime.bc.ca>
+
+	* asm.h, rtems/new-exceptions/cpu.h, rtems/score/ppc.h: addition of
+	MPC555 support as part of the addition of the SS555 BSP.
+
 2004-04-06	Ralf Corsepius <ralf_corsepius@rtems.org>
 
 	* configure.ac: Remove (Merged into $(top_srcdir)/configure.ac).
diff --git a/cpukit/score/cpu/powerpc/asm.h b/cpukit/score/cpu/powerpc/asm.h
index 419202eb26..74dc28e57d 100644
--- a/cpukit/score/cpu/powerpc/asm.h
+++ b/cpukit/score/cpu/powerpc/asm.h
@@ -203,6 +203,12 @@
 #define br7     0x087   /* DCR: memory bank register 7             */
 /* end of IBM400 series register definitions */
 
+#elif defined(mpc555)
+/* The following registers are for the MPC5xx */
+#define eie     0x050   /* External Interrupt Enable Register */
+#define eid     0x051   /* External Interrupt Disable Register */
+#define nri     0x052   /* Non-Recoverable Interrupt Register */ 
+  
 #elif defined(mpc860) || defined(mpc821)
 /* The following registers are for the MPC8x0 */
 #define der     0x095   /* Debug Enable Register */
diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h
index 419202eb26..74dc28e57d 100644
--- a/cpukit/score/cpu/powerpc/rtems/asm.h
+++ b/cpukit/score/cpu/powerpc/rtems/asm.h
@@ -203,6 +203,12 @@
 #define br7     0x087   /* DCR: memory bank register 7             */
 /* end of IBM400 series register definitions */
 
+#elif defined(mpc555)
+/* The following registers are for the MPC5xx */
+#define eie     0x050   /* External Interrupt Enable Register */
+#define eid     0x051   /* External Interrupt Disable Register */
+#define nri     0x052   /* Non-Recoverable Interrupt Register */ 
+  
 #elif defined(mpc860) || defined(mpc821)
 /* The following registers are for the MPC8x0 */
 #define der     0x095   /* Debug Enable Register */
diff --git a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
index 5583cca0c6..23b685c235 100644
--- a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
@@ -414,7 +414,7 @@ typedef struct {
   boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
 #endif
 
-#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
+#if (defined(mpc555) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
   uint32_t     clock_speed;            /* Speed of CPU in Hz */
 #endif
 }   rtems_cpu_table;
diff --git a/cpukit/score/cpu/powerpc/rtems/score/ppc.h b/cpukit/score/cpu/powerpc/rtems/score/ppc.h
index 698dfd4781..0bdb0c010c 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/ppc.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/ppc.h
@@ -123,6 +123,9 @@ extern "C" {
 #define PPC_ALIGNMENT		4
 #define PPC_CACHE_ALIGNMENT	16
 
+/* Added by querbach@realtime.bc.ca */
+#define PPC_LOW_POWER_MODE	PPC_LOW_POWER_MODE_STANDARD
+
 /* Based on comments by Sergei Organov <osv@Javad.RU> */
 #define PPC_I_CACHE        	0 
 #define PPC_D_CACHE        	0 
@@ -496,6 +499,16 @@ extern "C" {
 #define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
 #define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
 
+#elif defined(mpc555)
+#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
+#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
+#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
+#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
+#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
+#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
+#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
+#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
+
 #elif defined(ppc601)
 #define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
 #define PPC_IRQ_LAST     PPC_IRQ_TRACE