diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-23 09:04:19 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-05-27 12:49:13 +0200 |
| commit | 18e1e5bbf11e637c7aa40ac12e4e9bd109df677b (patch) | |
| tree | d2ac9617407fff20c60ce11b26d849d25d5f427c /cpukit | |
| parent | dosfs: Add RTEMS_DOSFS_SEMAPHORES_PER_INSTANCE (diff) | |
| download | rtems-18e1e5bbf11e637c7aa40ac12e4e9bd109df677b.tar.bz2 | |
arm: Fix CPSR and SPSR access
The GNU assembler translates for example a
msr spsr, rN
into
msr SPSR_fc, rN
This would update only a subset of the register and leads to an
incomplete exceptions restore sequence resulting in system corruption.
Correct is this:
msr SPSR_fsxc, rN
Diffstat (limited to 'cpukit')
| -rw-r--r-- | cpukit/score/cpu/arm/arm_exc_interrupt.S | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/arm/cpu_asm.S | 4 |
2 files changed, 8 insertions, 8 deletions
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S index a1363e571e..708af229f1 100644 --- a/cpukit/score/cpu/arm/arm_exc_interrupt.S +++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S @@ -63,13 +63,13 @@ _ARMV4_Exception_interrupt: /* Set exchange registers */ mov EXCHANGE_LR, lr - mrs EXCHANGE_SPSR, spsr - mrs EXCHANGE_CPSR, cpsr + mrs EXCHANGE_SPSR, SPSR + mrs EXCHANGE_CPSR, CPSR sub EXCHANGE_INT_SP, sp, #EXCHANGE_SIZE /* Switch to SVC mode */ orr EXCHANGE_CPSR, EXCHANGE_CPSR, #0x1 - msr cpsr, EXCHANGE_CPSR + msr CPSR_c, EXCHANGE_CPSR /* * Save context. We save the LR separately because it has to be @@ -183,11 +183,11 @@ thread_dispatch_done: add sp, #CONTEXT_SIZE /* Get INT mode program status register */ - mrs r1, cpsr + mrs r1, CPSR bic r1, r1, #0x1 /* Switch to INT mode */ - msr cpsr, r1 + msr CPSR_c, r1 /* Save EXCHANGE_LR and EXCHANGE_SPSR registers to exchange area */ stmdb sp!, {EXCHANGE_LR, EXCHANGE_SPSR} @@ -197,7 +197,7 @@ thread_dispatch_done: /* Set return address and program status */ mov lr, EXCHANGE_LR - msr spsr, EXCHANGE_SPSR + msr SPSR_fsxc, EXCHANGE_SPSR /* Restore EXCHANGE_LR and EXCHANGE_SPSR registers from exchange area */ ldmia sp!, {EXCHANGE_LR, EXCHANGE_SPSR} diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S index 22dd7a34b5..af8f1531b6 100644 --- a/cpukit/score/cpu/arm/cpu_asm.S +++ b/cpukit/score/cpu/arm/cpu_asm.S @@ -54,7 +54,7 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch) /* Start saving context */ - mrs r2, cpsr + mrs r2, CPSR stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} #ifdef ARM_MULTILIB_VFP_D32 @@ -71,7 +71,7 @@ _restore: #endif ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14} - msr cpsr, r2 + msr CPSR_fsxc, r2 #ifdef __thumb__ bx lr nop |