PR 1993 - Convert MIPS to PIC IRQ model

3 files changed, 34 insertions, 77 deletions

diff --git a/cpukit/score/cpu/mips/ChangeLog b/cpukit/score/cpu/mips/ChangeLog
index 765b4ab280..98cff7f8d4 100644
--- a/cpukit/score/cpu/mips/ChangeLog
+++ b/cpukit/score/cpu/mips/ChangeLog
@@ -1,3 +1,15 @@
+2012-03-07	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	* rtems/score/cpu.h: In order to handle a issue in the 
+	compilation of printk all tasks should be defined as 
+	floating point for the MIPS processor.
+
+2012-02-23	Jennifer Averett <Jennifer.Averett@OARcorp.com>
+
+	PR 1993/bsps
+	* cpu.c, rtems/score/cpu.h:
+	Mips conversion to PIC IRQ model.
+
 2011-12-09	Jennifer Averett
 
 	* cpu.c: Correct typo.
diff --git a/cpukit/score/cpu/mips/cpu.c b/cpukit/score/cpu/mips/cpu.c
index 4e41c91013..ffb1e66ca8 100644
--- a/cpukit/score/cpu/mips/cpu.c
+++ b/cpukit/score/cpu/mips/cpu.c
@@ -1,4 +1,6 @@
-/*
+/**
+ *  @file
+ *  
  *  Mips CPU Dependent Source
  *
  *  2002:       Greg Menke (gregory.menke@gsfc.nasa.gov)
@@ -17,7 +19,9 @@
  *    wrote the JMR3904 BSP so this could be tested.  Joel also
  *    added the new interrupt vectoring support in libcpu and
  *    tried to better support the various interrupt controllers.
- *
+ */
+
+/*
  *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
  *           COPYRIGHT (c) 1996 by Transition Networks Inc.
  *
@@ -32,13 +36,13 @@
  *             Transition Networks makes no representations about the
  *             suitability of this software for any purpose.
  *
- *  COPYRIGHT (c) 1989-2001.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- *
+ * 
  *  $Id$
  */
 
@@ -170,74 +174,6 @@ void _CPU_ISR_Set_level( uint32_t   new_level )
   mips_set_sr( sr );
 }
 
-
-
-/*
- *  _CPU_ISR_install_raw_handler
- *
- *  Input parameters:
- *    vector      - interrupt vector number
- *    old_handler - former ISR for this vector number
- *    new_handler - replacement ISR for this vector number
- *
- *  Output parameters:  NONE
- *
- */
-
-void _CPU_ISR_install_raw_handler(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-  /*
-   *  This is where we install the interrupt handler into the "raw" interrupt
-   *  table used by the CPU to dispatch interrupt handlers.
-   *
-   *  Because all interrupts are vectored through the same exception handler
-   *  this is not necessary on this port.
-   */
-}
-
-/*
- *  _CPU_ISR_install_vector
- *
- *  This kernel routine installs the RTEMS handler for the
- *  specified vector.
- *
- *  Input parameters:
- *    vector      - interrupt vector number
- *    old_handler - former ISR for this vector number
- *    new_handler - replacement ISR for this vector number
- *
- *  Output parameters:  NONE
- *
- */
-
-void _CPU_ISR_install_vector(
-  uint32_t    vector,
-  proc_ptr    new_handler,
-  proc_ptr   *old_handler
-)
-{
-   *old_handler = _ISR_Vector_table[ vector ];
-
-   /*
-    *  If the interrupt vector table is a table of pointer to isr entry
-    *  points, then we need to install the appropriate RTEMS interrupt
-    *  handler for this vector number.
-    */
-
-   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
-
-   /*
-    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
-    *  be used by the _ISR_Handler so the user gets control.
-    */
-
-    _ISR_Vector_table[ vector ] = new_handler;
-}
-
 /*
  *  _CPU_Install_interrupt_stack
  */
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index f626636dab..8215d346b5 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -1,4 +1,6 @@
-/*
+/**
+ *  @file
+ *  
  *  Mips CPU Dependent Header File
  *
  *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
@@ -12,6 +14,9 @@
  *    added the new interrupt vectoring support in libcpu and
  *    tried to better support the various interrupt controllers.
  *
+ */
+
+/*
  *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
  *           COPYRIGHT (c) 1996 by Transition Networks Inc.
  *
@@ -26,13 +31,13 @@
  *      Transition Networks makes no representations about the suitability
  *      of this software for any purpose.
  *
- *  COPYRIGHT (c) 1989-2006.
+ *  COPYRIGHT (c) 1989-2012.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
- *
+ * 
  *  $Id$
  */
 
@@ -124,7 +129,7 @@ extern "C" {
  *
  *  XXX document implementation including references if appropriate
  */
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
 
 /*
  *  Does this CPU have hardware support for a dedicated interrupt stack?
@@ -201,9 +206,13 @@ extern "C" {
  *  In this case, this option should be TRUE.
  *
  *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ *  Mips Note: It appears the GCC can implicitly generate FPU
+ *  and Altivec instructions when you least expect them.  So make
+ *  all tasks floating point.
  */
 
-#define CPU_ALL_TASKS_ARE_FP    FALSE
+#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 
 
 /*
  *  Should the IDLE task have a floating point context?