2011-02-11 Ralf Corsépius <ralf.corsepius@rtems.org>

	* cpu.c, irq.c, rtems/score/lm32.h:
	Use "__asm__" instead of "asm" for improved c99-compliance.

4 files changed, 18 insertions, 13 deletions

diff --git a/cpukit/score/cpu/lm32/ChangeLog b/cpukit/score/cpu/lm32/ChangeLog
index 318ca790f6..f814148063 100644
--- a/cpukit/score/cpu/lm32/ChangeLog
+++ b/cpukit/score/cpu/lm32/ChangeLog
@@ -1,3 +1,8 @@
+2011-02-11	Ralf Corsépius <ralf.corsepius@rtems.org>
+
+	* cpu.c, irq.c, rtems/score/lm32.h:
+	Use "__asm__" instead of "asm" for improved c99-compliance.
+
 2010-10-21	Joel Sherrill <joel.sherrill@oarcorp.com>
 
 	* rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
diff --git a/cpukit/score/cpu/lm32/cpu.c b/cpukit/score/cpu/lm32/cpu.c
index 73bc7c38e9..1b90d2f561 100644
--- a/cpukit/score/cpu/lm32/cpu.c
+++ b/cpukit/score/cpu/lm32/cpu.c
@@ -169,6 +169,6 @@ void *_CPU_Thread_Idle_body( uintptr_t ignored )
     /* The LM32 softcore itself hasn't any HLT instruction. But the
      * LM32 qemu target interprets this nop instruction as HLT.
      */
-    asm volatile("and r0, r0, r0");
+    __asm__ volatile("and r0, r0, r0");
  }
 }
diff --git a/cpukit/score/cpu/lm32/irq.c b/cpukit/score/cpu/lm32/irq.c
index fbe5fecdd2..a6fe8fd18b 100644
--- a/cpukit/score/cpu/lm32/irq.c
+++ b/cpukit/score/cpu/lm32/irq.c
@@ -35,7 +35,7 @@
 
 void *_exception_stack_frame;
 
-register unsigned long  *stack_ptr asm("sp");
+register unsigned long  *stack_ptr __asm__ ("sp");
 
 void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
 {
diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h
index 5255115403..328e6dff59 100644
--- a/cpukit/score/cpu/lm32/rtems/score/lm32.h
+++ b/cpukit/score/cpu/lm32/rtems/score/lm32.h
@@ -69,43 +69,43 @@ extern "C" {
 #endif
 
 #define lm32_read_interrupts( _ip) \
-  asm volatile ("rcsr %0, ip":"=r"(_ip));
+  __asm__ volatile ("rcsr %0, ip":"=r"(_ip));
 
 #define lm32_disable_interrupts( _level ) \
   do { register uint32_t ie; \
-    asm volatile ("rcsr %0,ie":"=r"(ie)); \
+    __asm__ volatile ("rcsr %0,ie":"=r"(ie)); \
     _level = ie; \
     ie &= (~0x0001); \
-    asm volatile ("wcsr ie,%0"::"r"(ie)); \
+    __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \
   } while (0)
 
 #define lm32_enable_interrupts( _level ) \
-  asm volatile ("wcsr ie,%0"::"r"(_level));
+  __asm__ volatile ("wcsr ie,%0"::"r"(_level));
 
 #define lm32_flash_interrupts( _level ) \
   do { register uint32_t ie; \
-    asm volatile ("wcsr ie,%0"::"r"(_level)); \
+    __asm__ volatile ("wcsr ie,%0"::"r"(_level)); \
     ie = _level & (~0x0001); \
-    asm volatile ("wcsr ie,%0"::"r"(ie)); \
+    __asm__ volatile ("wcsr ie,%0"::"r"(ie)); \
   } while (0)
 
 #define lm32_interrupt_unmask( _mask ) \
   do { register uint32_t im; \
-    asm volatile ("rcsr %0,im":"=r"(im)); \
+    __asm__ volatile ("rcsr %0,im":"=r"(im)); \
     im |= _mask; \
-    asm volatile ("wcsr im,%0"::"r"(im)); \
+    __asm__ volatile ("wcsr im,%0"::"r"(im)); \
   } while (0)
 
 #define lm32_interrupt_mask( _mask ) \
   do { register uint32_t im; \
-    asm volatile ("rcsr %0,im":"=r"(im)); \
+    __asm__ volatile ("rcsr %0,im":"=r"(im)); \
     im &= ~_mask; \
-    asm volatile ("wcsr im,%0"::"r"(im)); \
+    __asm__ volatile ("wcsr im,%0"::"r"(im)); \
   } while (0)
 
 #define lm32_interrupt_ack( _mask ) \
   do { register uint32_t ip = _mask; \
-    asm volatile ("wcsr ip,%0"::"r"(ip)); \
+    __asm__ volatile ("wcsr ip,%0"::"r"(ip)); \
   } while (0)
 
 #endif /* _RTEMS_SCORE_LM32_H */