adapted for modified exception code

4 files changed, 117 insertions, 40 deletions

diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog
index bb7cd0bd03..431492b5a7 100644
--- a/cpukit/score/cpu/powerpc/ChangeLog
+++ b/cpukit/score/cpu/powerpc/ChangeLog
@@ -1,3 +1,24 @@
+2008-07-10	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* rtems/asm.h: Added defines for save and restore registers and
+	special purpose registers 4 to 7.
+
+	* rtems/new-exceptions/cpu.h: Changed define PPC_BSP_HAS_FIXED_PR288 to
+	a value that results in a compile time error on usage since SPRG0 is
+	now used for the interrupt disable mask.
+
+	* rtems/powerpc/registers.h: Bugfix: Swapped values of TBWU and TBWL.
+
+	Added defines SPRG4..7 and USPRG0.
+
+	Changed _CPU_ISR_{Disable, Enable, Flush} to use static inline
+	functions.  The interrupt disable mask is now stored in SPRG0.  Which
+	was previously denoted to indicate a PR288 bugfix.  You may now
+	initialize the interrupt disable mask via
+	ppc_interrupt_set_disable_mask() and
+	PPC_INTERRUPT_DISABLE_MASK_DEFAULT.  The default value will be set in
+	bootcard.c.
+
 2008-02-20	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* rtems/old-exceptions/cpu.h: Remove (Abandoned).
diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h
index b115d26c5a..1afc422d31 100644
--- a/cpukit/score/cpu/powerpc/rtems/asm.h
+++ b/cpukit/score/cpu/powerpc/rtems/asm.h
@@ -157,15 +157,25 @@
  */
 #define srr0	0x01a
 #define srr1	0x01b
-#if defined(ppc403) || defined(ppc405)
-#define srr2	0x3de	/* IBM 400 series only */
-#define srr3	0x3df	/* IBM 400 series only */
-#endif /* ppc403 or ppc405 */
+#define srr2	0x3de /* IBM 400 series only */
+#define srr3	0x3df /* IBM 400 series only */
+#define csrr0	58 /* Book E */
+#define csrr1	59 /* Book E */
+#define mcsrr0	570 /* e500 */
+#define mcsrr1	571 /* e500 */
+#define dsrr0	574 /* e200 */
+#define dsrr1	575 /* e200 */
 
 #define sprg0	0x110
 #define sprg1	0x111
 #define sprg2	0x112
 #define sprg3	0x113
+#define sprg4	276
+#define sprg5	277
+#define sprg6	278
+#define sprg7	279
+
+#define usprg0	256
 
 #define dar     0x013   /* Data Address Register */
 #define dec		0x016	/* Decrementer Register */
diff --git a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
index 71d514cc72..8316237207 100644
--- a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h
@@ -311,15 +311,11 @@ void _BSP_Fatal_error(unsigned int);
 /* end of Fatal Error manager macros */
 
 /*
- *  Until all new-exception processing BSPs have fixed
- *  PR288, we let the good BSPs pass
- *
- *  PPC_BSP_HAS_FIXED_PR288
- *
- *  in SPRG0 and let _CPU_Initialize assert this.
+ * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
+ * Now SPRG0 is devoted to the interrupt disable mask.
  */
 
-#define PPC_BSP_HAS_FIXED_PR288	0x600dbabe
+#define PPC_BSP_HAS_FIXED_PR288	ppc_this_is_now_the_interrupt_disable_mask
 
 #endif /* ASM */
 
diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index 3153545b8f..05d429e239 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -18,10 +18,6 @@
 #ifndef _RTEMS_POWERPC_REGISTERS_H
 #define _RTEMS_POWERPC_REGISTERS_H
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 /* Bit encodings for Machine State Register (MSR) */
 #define MSR_VE		(1<<25)		/* Alti-Vec enable (7400+) */
 #define MSR_POW		(1<<18)		/* Enable Power Management */
@@ -37,6 +33,7 @@ extern "C" {
 #define MSR_BE		(1<<9)		/* Branch Trace */
 #define MSR_DE		(1<<9)		/* BookE debug exception */
 #define MSR_FE1		(1<<8)		/* Floating Exception mode 1 */
+#define MSR_E300_CE	(1<<7)		/* e300 critical interrupt */
 #define MSR_IP		(1<<6)		/* Exception prefix 0x000/0xFFF */
 #define MSR_IR		(1<<5)		/* Instruction MMU enable */
 #define MSR_DR		(1<<4)		/* Data MMU enable */
@@ -120,8 +117,8 @@ n:
 
 #define	TBRU	269	/* Time base Upper/Lower (Reading) */
 #define	TBRL	268
-#define TBWU	284	/* Time base Upper/Lower (Writing) */
-#define TBWL	285
+#define TBWU	285	/* Time base Upper/Lower (Writing) */
+#define TBWL	284
 #define	XER	1
 #define LR	8
 #define CTR	9
@@ -184,6 +181,11 @@ n:
 #define SPRG2   274
 #define SPR3	275
 #define SPRG3   275
+#define SPRG4   276
+#define SPRG5   277
+#define SPRG6   278
+#define SPRG7   279
+#define USPRG0  256
 #define DSISR	18
 #define SRR0	26	/* Saved Registers (exception) */
 #define SRR1	27
@@ -307,6 +309,22 @@ lidate */
 #define BOOKE_TCR_WPEXT(x)	(((x)&0xf)<<17)
 #define BOOKE_TCR_FPEXT(x)	(((x)&0xf)<<13)
 
+/**
+ * @brief Default value for the interrupt disable mask.
+ *
+ * The interrupt disable mask is stored in the SPRG0 (= special purpose
+ * register 272).
+ */
+#define PPC_INTERRUPT_DISABLE_MASK_DEFAULT MSR_EE
+
+#ifndef ASM
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
 #define _CPU_MSR_GET( _msr_value ) \
   do { \
     _msr_value = 0; \
@@ -316,16 +334,57 @@ lidate */
 #define _CPU_MSR_SET( _msr_value ) \
 { asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
 
-#define _CPU_ISR_Disable( _isr_cookie ) \
-  { register unsigned int _disable_mask = MSR_EE; \
-    _isr_cookie = 0; \
-    asm volatile ( \
-	"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
-	"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
-	"0" ((_isr_cookie)), "1" ((_disable_mask)) \
-	); \
-  }
+static inline void ppc_interrupt_set_disable_mask( uint32_t mask)
+{
+  asm volatile (
+    "mtspr 272, %0"
+    :
+    : "r" (mask)
+  );
+}
 
+static inline uint32_t ppc_interrupt_disable()
+{
+  uint32_t level;
+  uint32_t mask;
+
+  asm volatile (
+    "mfmsr %0;"
+    "mfspr %1, 272;"
+    "andc %1, %0, %1;"
+    "mtmsr %1"
+    : "=r" (level), "=r" (mask)
+  );
+
+  return level;
+}
+
+static inline void ppc_interrupt_enable( uint32_t level)
+{
+  asm volatile (
+    "mtmsr %0"
+    :
+    : "r" (level)
+  );
+}
+
+static inline void ppc_interrupt_flash( uint32_t level)
+{
+  uint32_t current_level;
+
+  asm volatile (
+    "mfmsr %0;"
+    "mtmsr %1;"
+    "mtmsr %0"
+    : "=&r" (current_level)
+    : "r" (level)
+  );
+}
+
+#define _CPU_ISR_Disable( _isr_cookie ) \
+  do { \
+    _isr_cookie = ppc_interrupt_disable(); \
+  } while (0)
 
 /*
  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
@@ -334,11 +393,7 @@ lidate */
  */
 
 #define _CPU_ISR_Enable( _isr_cookie )  \
-  { \
-     asm volatile ( "mtmsr %0" : \
-		   "=r" ((_isr_cookie)) : \
-                   "0" ((_isr_cookie))); \
-  }
+  ppc_interrupt_enable( _isr_cookie)
 
 /*
  *  This temporarily restores the interrupt to _isr_cookie before immediately
@@ -352,19 +407,14 @@ lidate */
  */
 
 #define _CPU_ISR_Flash( _isr_cookie ) \
-  { register unsigned int _disable_mask = MSR_EE; \
-    asm volatile ( \
-      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
-      "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
-      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
-    ); \
-  }
-
+  ppc_interrupt_flash( _isr_cookie)
 
 /* end of ISR handler macros */
 
 #ifdef __cplusplus
 }
-#endif
+#endif /* __cplusplus */
+
+#endif /* ASM */
 
 #endif /* _RTEMS_POWERPC_REGISTERS_H */