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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-05 14:54:11 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-09 23:02:38 +0200 |
commit | d19cce29dcaffa7c679407bc211ee09c2d9dc40a (patch) | |
tree | 2e0eb6211f0199680fcf9445b644a25495e53732 /cpukit/score/src/threadhandler.c | |
parent | score: Add and use _Per_CPU_Acquire_all(). (diff) | |
download | rtems-d19cce29dcaffa7c679407bc211ee09c2d9dc40a.tar.bz2 |
score: Per-CPU thread dispatch disable level
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
Diffstat (limited to 'cpukit/score/src/threadhandler.c')
-rw-r--r-- | cpukit/score/src/threadhandler.c | 90 |
1 files changed, 73 insertions, 17 deletions
diff --git a/cpukit/score/src/threadhandler.c b/cpukit/score/src/threadhandler.c index 1fde4cd4e5..80941f82de 100644 --- a/cpukit/score/src/threadhandler.c +++ b/cpukit/score/src/threadhandler.c @@ -19,6 +19,7 @@ #endif #include <rtems/score/threadimpl.h> +#include <rtems/score/assert.h> #include <rtems/score/interr.h> #include <rtems/score/isrlevel.h> #include <rtems/score/userextimpl.h> @@ -46,12 +47,46 @@ #define EXECUTE_GLOBAL_CONSTRUCTORS #endif +#if defined(EXECUTE_GLOBAL_CONSTRUCTORS) + static bool _Thread_Handler_is_constructor_execution_required( + Thread_Control *executing + ) + { + static bool doneConstructors; + bool doCons = false; + + #if defined(RTEMS_SMP) + static SMP_lock_Control constructor_lock = SMP_LOCK_INITIALIZER; + + if ( !doneConstructors ) { + _SMP_lock_Acquire( &constructor_lock ); + #endif + + #if defined(RTEMS_MULTIPROCESSING) + doCons = !doneConstructors + && _Objects_Get_API( executing->Object.id ) != OBJECTS_INTERNAL_API; + if (doCons) + doneConstructors = true; + #else + (void) executing; + doCons = !doneConstructors; + doneConstructors = true; + #endif + + #if defined(RTEMS_SMP) + _SMP_lock_Release( &constructor_lock ); + } + #endif + + return doCons; + } +#endif + void _Thread_Handler( void ) { ISR_Level level; Thread_Control *executing; #if defined(EXECUTE_GLOBAL_CONSTRUCTORS) - static bool doneConstructors; bool doCons; #endif @@ -64,23 +99,17 @@ void _Thread_Handler( void ) */ _Context_Initialization_at_thread_begin(); - /* - * have to put level into a register for those cpu's that use - * inline asm here - */ - level = executing->Start.isr_level; - _ISR_Set_level(level); + #if !defined(RTEMS_SMP) + /* + * have to put level into a register for those cpu's that use + * inline asm here + */ + level = executing->Start.isr_level; + _ISR_Set_level( level ); + #endif #if defined(EXECUTE_GLOBAL_CONSTRUCTORS) - #if defined(RTEMS_MULTIPROCESSING) - doCons = !doneConstructors - && _Objects_Get_API( executing->Object.id ) != OBJECTS_INTERNAL_API; - if (doCons) - doneConstructors = true; - #else - doCons = !doneConstructors; - doneConstructors = true; - #endif + doCons = _Thread_Handler_is_constructor_execution_required( executing ); #endif /* @@ -109,7 +138,34 @@ void _Thread_Handler( void ) /* * At this point, the dispatch disable level BETTER be 1. */ - _Thread_Enable_dispatch(); + #if defined(RTEMS_SMP) + { + /* + * On SMP we enter _Thread_Handler() with interrupts disabled and + * _Thread_Dispatch() obtained the per-CPU lock for us. We have to + * release it here and set the desired interrupt level of the thread. + */ + Per_CPU_Control *per_cpu = _Per_CPU_Get(); + + _Assert( per_cpu->thread_dispatch_disable_level == 1 ); + _Assert( _ISR_Get_level() != 0 ); + + per_cpu->thread_dispatch_disable_level = 0; + + _Per_CPU_Release( per_cpu ); + + level = executing->Start.isr_level; + _ISR_Set_level( level); + + /* + * The thread dispatch level changed from one to zero. Make sure we lose + * no thread dispatch necessary update. + */ + _Thread_Dispatch(); + } + #else + _Thread_Enable_dispatch(); + #endif #if defined(EXECUTE_GLOBAL_CONSTRUCTORS) /* |