score: Add local context to SMP lock API

Add a local context structure to the SMP lock API for acquire and
release pairs.  This context can be used to store the ISR level and
profiling information.  It may be later used to enable more
sophisticated lock algorithms, e.g. MCS locks.

There is only one lock that cannot be used with a local context.  This
is the per-CPU lock since here we would have to transfer the local
context through a context switch which is very complicated.

1 files changed, 15 insertions, 15 deletions

diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c
index b6eb49f48a..dc03a702a4 100644
--- a/cpukit/score/src/threaddispatchdisablelevel.c
+++ b/cpukit/score/src/threaddispatchdisablelevel.c
@@ -33,12 +33,13 @@ static Giant_Control _Giant = {
   .nest_level = 0
 };
 
-static void _Giant_Do_acquire( uint32_t self_cpu_index )
+static void _Giant_Do_acquire( Per_CPU_Control *self_cpu )
 {
   Giant_Control *giant = &_Giant;
+  uint32_t self_cpu_index = _Per_CPU_Get_index( self_cpu );
 
   if ( giant->owner_cpu != self_cpu_index ) {
-    _SMP_lock_Acquire( &giant->lock );
+    _SMP_lock_Acquire( &giant->lock, &self_cpu->Giant_lock_context );
     giant->owner_cpu = self_cpu_index;
     giant->nest_level = 1;
   } else {
@@ -46,48 +47,47 @@ static void _Giant_Do_acquire( uint32_t self_cpu_index )
   }
 }
 
-static void _Giant_Do_release( void )
+static void _Giant_Do_release( Per_CPU_Control *self_cpu )
 {
   Giant_Control *giant = &_Giant;
 
   --giant->nest_level;
   if ( giant->nest_level == 0 ) {
     giant->owner_cpu = NO_OWNER_CPU;
-    _SMP_lock_Release( &giant->lock );
+    _SMP_lock_Release( &giant->lock, &self_cpu->Giant_lock_context );
   }
 }
 
-void _Giant_Drop( uint32_t self_cpu )
+void _Giant_Drop( Per_CPU_Control *self_cpu )
 {
   Giant_Control *giant = &_Giant;
+  uint32_t self_cpu_index = _Per_CPU_Get_index( self_cpu );
 
   _Assert( _ISR_Get_level() != 0 );
 
-  if ( giant->owner_cpu == self_cpu ) {
+  if ( giant->owner_cpu == self_cpu_index ) {
     giant->nest_level = 0;
     giant->owner_cpu = NO_OWNER_CPU;
-    _SMP_lock_Release( &giant->lock );
+    _SMP_lock_Release( &giant->lock, &self_cpu->Giant_lock_context );
   }
 }
 
 uint32_t _Thread_Dispatch_increment_disable_level( void )
 {
   ISR_Level isr_level;
-  uint32_t self_cpu_index;
   uint32_t disable_level;
   Per_CPU_Control *self_cpu;
 
   _ISR_Disable_without_giant( isr_level );
 
   /*
-   * We must obtain the processor ID after interrupts are disabled to prevent
+   * We must obtain the processor after interrupts are disabled to prevent
    * thread migration.
    */
-  self_cpu_index = _SMP_Get_current_processor();
+  self_cpu = _Per_CPU_Get();
 
-  _Giant_Do_acquire( self_cpu_index );
+  _Giant_Do_acquire( self_cpu );
 
-  self_cpu = _Per_CPU_Get_by_index( self_cpu_index );
   disable_level = self_cpu->thread_dispatch_disable_level;
   ++disable_level;
   self_cpu->thread_dispatch_disable_level = disable_level;
@@ -110,7 +110,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
   --disable_level;
   self_cpu->thread_dispatch_disable_level = disable_level;
 
-  _Giant_Do_release();
+  _Giant_Do_release( self_cpu );
   _Assert( disable_level != 0 || _Giant.owner_cpu == NO_OWNER_CPU );
 
   _ISR_Enable_without_giant( isr_level );
@@ -124,7 +124,7 @@ void _Giant_Acquire( void )
 
   _ISR_Disable_without_giant( isr_level );
   _Assert( _Thread_Dispatch_disable_level != 0 );
-  _Giant_Do_acquire( _SMP_Get_current_processor() );
+  _Giant_Do_acquire( _Per_CPU_Get() );
   _ISR_Enable_without_giant( isr_level );
 }
 
@@ -134,7 +134,7 @@ void _Giant_Release( void )
 
   _ISR_Disable_without_giant( isr_level );
   _Assert( _Thread_Dispatch_disable_level != 0 );
-  _Giant_Do_release();
+  _Giant_Do_release( _Per_CPU_Get() );
   _ISR_Enable_without_giant( isr_level );
 }