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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-07-26 16:26:07 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-07-30 09:53:24 +0200 |
| commit | 21ff802c7f77dee09144b0a249fc0dc5d6ae0e2c (patch) | |
| tree | 999a23d683c63197ea5ab48c1be1378dfff560a5 /cpukit/score/src/threaddispatchdisablelevel.c | |
| parent | smp: Delete _ISR_SMP_Initialize() (diff) | |
| download | rtems-21ff802c7f77dee09144b0a249fc0dc5d6ae0e2c.tar.bz2 | |
smp: Delete _ISR_Disable_on_this_core(), etc.
Delete _ISR_Enable_on_this_core(), _ISR_Flash_on_this_core(),
_ISR_SMP_Disable(), _ISR_SMP_Enable(), _ISR_SMP_Flash().
The ISR disable/enable interface has no parameter to pass a specific
object. Thus it is only possible to implement a single global lock
object with this interface. Using the ISR disable/enable as the giant
lock on SMP configurations is not feasible.
Potentially blocking resource obtain sequences protected by the thread
dispatch disable level are subdivided into smaller ISR disabled critical
sections. This works since on single processor configurations there is
only one thread of execution that can block. On SMP this is different
(image a mutex obtained concurrently by different threads on different
processors).
The thread dispatch disable level is currently used as the giant lock.
There is not need to complicate things with this unused interface.
Diffstat (limited to 'cpukit/score/src/threaddispatchdisablelevel.c')
| -rw-r--r-- | cpukit/score/src/threaddispatchdisablelevel.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c index f1c971e33f..816959a1ca 100644 --- a/cpukit/score/src/threaddispatchdisablelevel.c +++ b/cpukit/score/src/threaddispatchdisablelevel.c @@ -49,7 +49,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void ) uint32_t self_cpu; uint32_t disable_level; - _ISR_Disable_on_this_core( isr_level ); + _ISR_Disable( isr_level ); /* * We must obtain the processor ID after interrupts are disabled since a @@ -69,7 +69,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void ) ++disable_level; _Thread_Dispatch_disable_level = disable_level; - _ISR_Enable_on_this_core( isr_level ); + _ISR_Enable( isr_level ); return disable_level; } @@ -81,7 +81,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void ) ISR_Level isr_level; uint32_t disable_level; - _ISR_Disable_on_this_core( isr_level ); + _ISR_Disable( isr_level ); disable_level = _Thread_Dispatch_disable_level; --disable_level; @@ -93,7 +93,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void ) _SMP_lock_Release( &level_lock->lock ); } - _ISR_Enable_on_this_core( isr_level ); + _ISR_Enable( isr_level ); return disable_level; } |