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authorJennifer Averett <Jennifer.Averett@OARcorp.com>2011-05-20 12:36:01 +0000
committerJennifer Averett <Jennifer.Averett@OARcorp.com>2011-05-20 12:36:01 +0000
commita8d7e2ab16f6c4a1a6e4f90010651b016ac6f7c1 (patch)
tree4123cb2913b2db3224b9c75ab8f9a49c60ea498c /cpukit/score/include
parent2011-05-20 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff)
downloadrtems-a8d7e2ab16f6c4a1a6e4f90010651b016ac6f7c1.tar.bz2
2011-05-20 Jennifer Averett <Jennifer.Averett@OARcorp.com>
PR 1787/cpukit * score/include/rtems/score/percpu.h, score/include/rtems/score/smplock.h, score/src/smp.c, score/src/smplock.c: Add nesting support to smp spinlock.
Diffstat (limited to 'cpukit/score/include')
-rw-r--r--cpukit/score/include/rtems/score/percpu.h7
-rw-r--r--cpukit/score/include/rtems/score/smplock.h85
2 files changed, 70 insertions, 22 deletions
diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h
index 9224ad0d2e..1ba5b3d6d2 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -92,18 +92,17 @@ typedef enum {
typedef struct {
#if defined(RTEMS_SMP)
/** This element is used to lock this structure */
- SMP_lock_Control lock;
+ SMP_lock_spinlock_simple_Control lock;
/** This indicates that the CPU is online. */
- uint32_t state;
+ uint32_t state;
/**
* This is the request for the interrupt.
*
* @note This may become a chain protected by atomic instructions.
*/
- uint32_t message;
-
+ uint32_t message;
#endif
#if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
diff --git a/cpukit/score/include/rtems/score/smplock.h b/cpukit/score/include/rtems/score/smplock.h
index a20d9260a4..279df6ecd8 100644
--- a/cpukit/score/include/rtems/score/smplock.h
+++ b/cpukit/score/include/rtems/score/smplock.h
@@ -34,10 +34,23 @@ extern "C" {
/**
* This type is used to lock elements for atomic access.
- *
- * @note This type may move to RTEMS.
+ * This spinlock is a simple non-nesting spinlock, and
+ * may be used for short non-nesting accesses.
+ */
+typedef uint32_t SMP_lock_spinlock_simple_Control;
+
+/**
+ * This type is used to lock elements for atomic access.
+ * This spinlock supports nesting, but is slightly more
+ * complicated to use. Please see the descriptions of
+ * obtain and release prior to using in order to understand
+ * the callers responsibilty of managing short interupt disable
+ * times.
*/
-typedef volatile uint32_t SMP_lock_Control;
+typedef struct {
+ uint32_t count;
+ int cpu_id;
+} SMP_lock_spinlock_nested_Control;
/**
* @brief Initialize a Lock
@@ -45,12 +58,9 @@ typedef volatile uint32_t SMP_lock_Control;
* This method is used to initialize the lock at @a lock.
*
* @param [in] lock is the address of the lock to obtain.
- *
- * @note This lock may be "too low" here. It may need to move
- * out of the BSP area.
*/
-void _SMP_lock_Spinlock_Initialize(
- SMP_lock_Control *lock
+void _SMP_lock_spinlock_simple_Initialize(
+ SMP_lock_spinlock_simple_Control *lock
);
/**
@@ -62,12 +72,9 @@ void _SMP_lock_Spinlock_Initialize(
*
* @return This method returns with processor interrupts disabled.
* The previous level is returned.
- *
- * @note This lock may be "too low" here. It may need to move
- * out of the BSP area.
*/
-ISR_Level _SMP_lock_Spinlock_Obtain(
- SMP_lock_Control *lock
+ISR_Level _SMP_lock_spinlock_simple_Obtain(
+ SMP_lock_spinlock_simple_Control *lock
);
/**
@@ -76,13 +83,55 @@ ISR_Level _SMP_lock_Spinlock_Obtain(
* This method is used to release the lock at @a lock.
*
* @param [in] lock is the address of the lock to obtain.
+ */
+void _SMP_lock_spinlock_simple_Release(
+ SMP_lock_spinlock_simple_Control *lock,
+ ISR_Level level
+);
+
+/**
+ * @brief Initialize a Lock
+ *
+ * This method is used to initialize the lock at @a lock.
+ *
+ * @param [in] lock is the address of the lock to obtain.
+ */
+void _SMP_lock_spinlock_nested_Initialize(
+ SMP_lock_spinlock_nested_Control *lock
+);
+
+/**
+ * @brief Obtain a Lock
+ *
+ * This method is used to obtain the lock at @a lock. ISR's are
+ * disabled when this routine returns and it is the callers responsibility
+ * to either:
+ * 1) Do something very short and then call
+ * _SMP_lock_spinlock_nested_Release or
+ * 2) Do something very sort, call isr enable, then when ready
+ * call isr_disable and _SMP_lock_spinlock_nested_Release
+ *
+ * @param [in] lock is the address of the lock to obtain.
*
- * @note This lock may be "too low" here. It may need to move
- * out of the BSP area.
+ * @return This method returns with processor interrupts disabled.
+ * The previous level is returned.
+ */
+ISR_Level _SMP_lock_spinlock_nested_Obtain(
+ SMP_lock_spinlock_nested_Control *lock
+);
+
+/**
+ * @brief Release a Lock
+ *
+ * This method is used to release the lock at @a lock. Note:
+ * ISR's are reenabled by this method and are expected to be
+ * disabled upon entry to the method.
+ *
+ * @param [in] lock is the address of the lock to obtain.
*/
-void _SMP_lock_Spinlock_Release(
- SMP_lock_Control *lock,
- ISR_Level level
+void _SMP_lock_spinlock_nested_Release(
+ SMP_lock_spinlock_nested_Control *lock,
+ ISR_Level level
);
#ifdef __cplusplus