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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-23 16:15:50 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-30 11:16:28 +0200 |
| commit | bf30999cc697325eda3afd1833b78a7e64255fc4 (patch) | |
| tree | bc365daf0a3c0e6fe7c72cfe33c7603f7da54351 /cpukit/score/include/rtems/score/isrlevel.h | |
| parent | sapi: SMP support for chains (diff) | |
| download | rtems-bf30999cc697325eda3afd1833b78a7e64255fc4.tar.bz2 | |
smp: Add and use _Assert_Owner_of_giant()
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Diffstat (limited to 'cpukit/score/include/rtems/score/isrlevel.h')
| -rw-r--r-- | cpukit/score/include/rtems/score/isrlevel.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h index 35d3d037cc..3da67fd189 100644 --- a/cpukit/score/include/rtems/score/isrlevel.h +++ b/cpukit/score/include/rtems/score/isrlevel.h @@ -20,6 +20,7 @@ #define _RTEMS_SCORE_ISR_LEVEL_h #include <rtems/score/cpu.h> +#include <rtems/score/assert.h> #ifdef __cplusplus extern "C" { @@ -57,6 +58,7 @@ typedef uint32_t ISR_Level; #define _ISR_Disable( _level ) \ do { \ _CPU_ISR_Disable( _level ); \ + _Assert_Owner_of_giant(); \ RTEMS_COMPILER_MEMORY_BARRIER(); \ } while (0) @@ -74,6 +76,7 @@ typedef uint32_t ISR_Level; #define _ISR_Enable( _level ) \ do { \ RTEMS_COMPILER_MEMORY_BARRIER(); \ + _Assert_Owner_of_giant(); \ _CPU_ISR_Enable( _level ); \ } while (0) @@ -99,6 +102,7 @@ typedef uint32_t ISR_Level; #define _ISR_Flash( _level ) \ do { \ RTEMS_COMPILER_MEMORY_BARRIER(); \ + _Assert_Owner_of_giant(); \ _CPU_ISR_Flash( _level ); \ RTEMS_COMPILER_MEMORY_BARRIER(); \ } while (0) @@ -132,6 +136,22 @@ typedef uint32_t ISR_Level; RTEMS_COMPILER_MEMORY_BARRIER(); \ } while (0) +#if defined( RTEMS_SMP ) + +#define _ISR_Disable_without_giant( _level ) \ + do { \ + _CPU_ISR_Disable( _level ); \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + } while (0) + +#define _ISR_Enable_without_giant( _level ) \ + do { \ + RTEMS_COMPILER_MEMORY_BARRIER(); \ + _CPU_ISR_Enable( _level ); \ + } while (0) + +#endif /* defined( RTEMS_SMP ) */ + /**@}*/ #ifdef __cplusplus |