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authorSebastian Huber <sebastian.huber@embedded-brains.de>2016-05-18 08:06:54 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2016-05-20 07:50:37 +0200
commit247131632173158cb2668d4e5c7464951b668067 (patch)
tree4242eb55b8a0721d94b01357195ef9441f561d18 /cpukit/score/include/rtems/score/isrlevel.h
parentscore: Rename _ISR_Disable_without_giant() (diff)
downloadrtems-247131632173158cb2668d4e5c7464951b668067.tar.bz2
score: Rename _ISR_Disable() and _ISR_Enable()
Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable() into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant(). This is a preparation to remove the Giant lock. Update #2555.
Diffstat (limited to 'cpukit/score/include/rtems/score/isrlevel.h')
-rw-r--r--cpukit/score/include/rtems/score/isrlevel.h25
1 files changed, 5 insertions, 20 deletions
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h
index cf8712a967..0eccd3aea1 100644
--- a/cpukit/score/include/rtems/score/isrlevel.h
+++ b/cpukit/score/include/rtems/score/isrlevel.h
@@ -55,10 +55,9 @@ typedef uint32_t ISR_Level;
* @param[out] _level The argument @a _level will contain the previous
* interrupt mask level.
*/
-#define _ISR_Disable( _level ) \
+#define _ISR_Local_disable( _level ) \
do { \
_CPU_ISR_Disable( _level ); \
- _Assert( _Debug_Is_owner_of_giant() ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
@@ -66,17 +65,16 @@ typedef uint32_t ISR_Level;
* @brief Enables interrupts on this processor.
*
* This macro restores the interrupt status on the processor with the
- * interrupt level value obtained by _ISR_Disable(). It is used at the end of
+ * interrupt level value obtained by _ISR_Local_disable(). It is used at the end of
* a critical section of code to enable interrupts so they can be processed
* again.
*
* @param[in] _level The interrupt level previously obtained by
- * _ISR_Disable().
+ * _ISR_Local_disable().
*/
-#define _ISR_Enable( _level ) \
+#define _ISR_Local_enable( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
- _Assert( _Debug_Is_owner_of_giant() ); \
_CPU_ISR_Enable( _level ); \
} while (0)
@@ -97,12 +95,11 @@ typedef uint32_t ISR_Level;
* properly protects itself.
*
* @param[in] _level The interrupt level previously obtained by
- * _ISR_Disable().
+ * _ISR_Local_disable().
*/
#define _ISR_Flash( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
- _Assert( _Debug_Is_owner_of_giant() ); \
_CPU_ISR_Flash( _level ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
@@ -136,18 +133,6 @@ typedef uint32_t ISR_Level;
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
-#define _ISR_Local_disable( _level ) \
- do { \
- _CPU_ISR_Disable( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- } while (0)
-
-#define _ISR_Local_enable( _level ) \
- do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Enable( _level ); \
- } while (0)
-
/**@}*/
#ifdef __cplusplus