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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-23 16:15:50 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-08-30 11:16:28 +0200 |
| commit | bf30999cc697325eda3afd1833b78a7e64255fc4 (patch) | |
| tree | bc365daf0a3c0e6fe7c72cfe33c7603f7da54351 /cpukit/score/include/rtems/score/isr.h | |
| parent | sapi: SMP support for chains (diff) | |
| download | rtems-bf30999cc697325eda3afd1833b78a7e64255fc4.tar.bz2 | |
smp: Add and use _Assert_Owner_of_giant()
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Diffstat (limited to 'cpukit/score/include/rtems/score/isr.h')
| -rw-r--r-- | cpukit/score/include/rtems/score/isr.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpukit/score/include/rtems/score/isr.h b/cpukit/score/include/rtems/score/isr.h index 4d4a5f3c49..fa0052fdcb 100644 --- a/cpukit/score/include/rtems/score/isr.h +++ b/cpukit/score/include/rtems/score/isr.h @@ -163,13 +163,13 @@ RTEMS_INLINE_ROUTINE uint32_t _ISR_Get_nest_level( void ) #if defined( RTEMS_SMP ) ISR_Level level; - _ISR_Disable( level ); + _ISR_Disable_without_giant( level ); #endif isr_nest_level = _ISR_Nest_level; #if defined( RTEMS_SMP ) - _ISR_Enable( level ); + _ISR_Enable_without_giant( level ); #endif return isr_nest_level; |