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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:34:12 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2010-06-29 00:34:12 +0000 |
| commit | 11e8bc5f0fa2d9485908874dbfe9cd65c1aec477 (patch) | |
| tree | 8e21888988f4c1e22aff26478e3f158e60c444c6 /cpukit/score/include/rtems/score/isr.h | |
| parent | 2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-11e8bc5f0fa2d9485908874dbfe9cd65c1aec477.tar.bz2 | |
2010-06-28 Joel Sherrill <joel.sherrill@oarcorp.com>
PR 1573/cpukit
* configure.ac, posix/src/killinfo.c,
posix/src/psignalclearprocesssignals.c,
posix/src/psignalsetprocesssignals.c,
posix/src/psignalunblockthread.c, posix/src/pthreadcreate.c,
posix/src/pthreadkill.c, posix/src/pthreadsigmask.c,
rtems/src/signalsend.c, rtems/src/taskmode.c, score/Makefile.am,
score/preinstall.am, score/include/rtems/system.h,
score/include/rtems/score/context.h, score/include/rtems/score/isr.h,
score/include/rtems/score/thread.h, score/src/isr.c,
score/src/isrthreaddispatch.c, score/src/thread.c,
score/src/threaddispatch.c, score/src/threadloadenv.c: Add a per cpu
data structure which contains the information required by RTEMS for
each CPU core. This encapsulates information such as thread
executing, heir, idle and dispatch needed.
* score/include/rtems/score/percpu.h, score/src/percpu.c: New files.
Diffstat (limited to 'cpukit/score/include/rtems/score/isr.h')
| -rw-r--r-- | cpukit/score/include/rtems/score/isr.h | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/cpukit/score/include/rtems/score/isr.h b/cpukit/score/include/rtems/score/isr.h index 66adbcb943..6f8096a2a9 100644 --- a/cpukit/score/include/rtems/score/isr.h +++ b/cpukit/score/include/rtems/score/isr.h @@ -21,11 +21,16 @@ #ifndef _RTEMS_SCORE_ISR_H #define _RTEMS_SCORE_ISR_H +#include <rtems/score/percpu.h> + /** * @defgroup ScoreISR ISR Handler * * This handler encapsulates functionality which provides the foundation * ISR services used in all of the APIs supported by RTEMS. + * + * The ISR Nest level counter variable is maintained as part of the + * per cpu data structure. */ /**@{*/ @@ -75,18 +80,6 @@ typedef ISR_Handler ( *ISR_Handler_entry )( */ #define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER -/** - * The following is true if signals have been sent to the currently - * executing thread by an ISR handler. - */ -SCORE_EXTERN bool _ISR_Signals_to_thread_executing; - -/** - * The following contains the interrupt service routine nest level. - * When this variable is zero, a thread is executing. - */ -SCORE_EXTERN volatile uint32_t _ISR_Nest_level; - #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE) /** * The following declares the Vector Table. Application |