2007-12-11 Joel Sherrill <joel.sherrill@OARcorp.com>

	* thumb_isr.c: Style.

2 files changed, 99 insertions, 89 deletions

diff --git a/cpukit/score/cpu/arm/thumb/ChangeLog b/cpukit/score/cpu/arm/thumb/ChangeLog
index 65ae8c8b69..ea6e9ead87 100644
--- a/cpukit/score/cpu/arm/thumb/ChangeLog
+++ b/cpukit/score/cpu/arm/thumb/ChangeLog
@@ -1,3 +1,7 @@
+2007-12-11	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* thumb_isr.c: Style.
+
 2007-11-26      Ray Xu <rayx.cn@gmail.com>
 
 	* thumb_isr.c: Remove extra debug information, Change function
diff --git a/cpukit/score/cpu/arm/thumb/thumb_isr.c b/cpukit/score/cpu/arm/thumb/thumb_isr.c
index 22915263f5..5b6ab7cd08 100644
--- a/cpukit/score/cpu/arm/thumb/thumb_isr.c
+++ b/cpukit/score/cpu/arm/thumb/thumb_isr.c
@@ -1,5 +1,5 @@
 /*
- *  The thumb mode do not support multi-level ISR, only disable and enable
+ *  Thumb mode does not support multi-level ISR, only disable and enable.
  *
  *  The license and distribution terms for this file may be
  *  found in the file LICENSE in this distribution or at
@@ -16,11 +16,11 @@
  *
  *  _CPU_ISR_Get_level_Thumb - returns the current interrupt level
  */
-uint32_t        _CPU_ISR_Get_level_Thumb(void)       __attribute__ ((naked));
-uint32_t    _CPU_ISR_Disable_Thumb(void )        __attribute__ ((naked));
-void    _CPU_ISR_Enable_Thumb(int  _level )  __attribute__ ((naked));
-void    _CPU_ISR_Flash_Thumb(int _level )    __attribute__ ((naked));
-void    _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
+uint32_t _CPU_ISR_Get_level_Thumb(void)       __attribute__ ((naked));
+uint32_t _CPU_ISR_Disable_Thumb(void )        __attribute__ ((naked));
+void     _CPU_ISR_Enable_Thumb(int  _level )  __attribute__ ((naked));
+void     _CPU_ISR_Flash_Thumb(int _level )    __attribute__ ((naked));
+void     _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
 
 /*
  * prevent multipule enable/disable ISR
@@ -32,7 +32,6 @@ void    _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
  * Set the CPSR bit 6,7 to 0 enables FIQ and IRQ
  */
 
-
 #define str(x) #x
 #define xstr(x) str(x)
 #define L(x) #x "_" xstr(__LINE__)
@@ -40,22 +39,22 @@ void    _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
 /*
  * Switch to ARM mode Veneer,ugly but safe
  */
-#define TO_ARM_MODE(x)		\
-	asm volatile (			\
-	".code	16			\n" \
-	L(x) "_thumb:		\n" \
-	".align 2			\n" \
-	"push {lr}			\n" \
-	"adr %0, "L(x) "_arm \n" \
-	"bl " L(x)" 		\n" \
-	"pop	{pc}		\n" \
-	".balign 4			\n" \
-	L(x) ":			    \n" \
-	"bx	%0		    	\n" \
-	"nop 				\n" \
-	".pool				\n" \
-	".code	32			\n" \
-	L(x) "_arm:			\n" \
+#define TO_ARM_MODE(x) \
+    asm volatile ( \
+        ".code  16           \n" \
+        L(x) "_thumb:        \n" \
+        ".align 2            \n" \
+        "push {lr}           \n" \
+        "adr %0, "L(x) "_arm \n" \
+        "bl " L(x)"          \n" \
+        "pop    {pc}         \n" \
+        ".balign 4           \n" \
+        L(x) ":              \n" \
+        "bx     %0           \n" \
+        "nop                 \n" \
+        ".pool               \n" \
+        ".code  32           \n" \
+        L(x) "_arm:          \n" \
     : "=&r" (reg))
 
 /*
@@ -64,64 +63,71 @@ void    _CPU_ISR_Set_level_Thumb(int  new_level )  __attribute__ ((naked));
  */
 
 uint32_t _CPU_ISR_Disable_Thumb(void )
-  {
-    int reg=0;
-    TO_ARM_MODE(disable);
-    asm volatile ( \
-		".code	32 				\n" \
-		"STMDB sp!, {r1}		\n" \
-		"MRS	r0, CPSR 		\n" \
-		"DISABLE_ARM:  			\n" \
-		"ORR  r1, r0, #0xc0 	\n"	\
-		"MSR  CPSR, r1 		\n" \
-		"pop  {r1}				\n" \
-		"BX LR 					\n" \
-		".code	16 				\n"	);
- }
+{
+  int reg=0;
+
+  TO_ARM_MODE(disable);
+  asm volatile( 
+      ".code  32             \n"
+      "STMDB sp!, {r1}       \n"
+      "MRS    r0, CPSR       \n"
+      "DISABLE_ARM:          \n"
+      "ORR  r1, r0, #0xc0    \n"
+      "MSR  CPSR, r1         \n"
+      "pop  {r1}             \n"
+      "BX LR                 \n"
+      ".code  16             \n"
+  );
+}
 
 /*
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable_Thumb).
+ *  Enable interrupts to the previous level (returned by
+ *  _CPU_ISR_Disable_Thumb).
  *  This indicates the end of an RTEMS critical section.  The parameter
  *  _level is not modified. I do not think _level is useful in this
  */
 
 void _CPU_ISR_Enable_Thumb(int  _level )
-  {
-  	int reg=0;
-  	TO_ARM_MODE(enable);
-	asm volatile ( \
-			".code	32			\n"	\
-			"ENABLE_ARM:  		\n" \
-			"MSR	CPSR, %0	\n"	\
-			/* Return back to thumb.*/	\
-			"BX 	R14 		\n" \
-			".code	16 			\n" \
-			: : "r"(_level));
-  }
+{
+  int reg=0;
+
+  TO_ARM_MODE(enable);
+  asm volatile(
+      ".code  32              \n"
+      "ENABLE_ARM:            \n"
+      "MSR    CPSR, %0        \n"
+      /* Return back to thumb.*/
+      "BX     R14             \n"
+      ".code  16              \n"
+      : : "r"(_level)
+  );
+}
 
 /*
  *  This temporarily restores the interrupt to _level before immediately
  *  disabling them again.  This is used to divide long RTEMS critical
  *  sections into two or more parts.  The parameter _level is not
- * modified.
+ *  modified.
  */
 void _CPU_ISR_Flash_Thumb(int _level )
-  {
-    int reg=0;
-    TO_ARM_MODE(flash);
-    asm volatile ( \
-			".code	32 			\n" \
-			"FLASH_ARM:  		\n" \
-			"MRS %0, CPSR		\n"	\
-			"BIC %0, %0, #0xC0	\n"	\
-			/* enable the irq*/		\
-			"MSR	CPSR_c, %0		\n"	\
-			"ORR	%0, %0, #0xc0	\n" \
-			"MSR	CPSR_c, %0		\n" \
-			"BX 	R14 			\n" \
-			".code	16 				\n" \
-			:"=&r"(reg) : "r" (_level));
-  }
+{
+  int reg=0;
+
+  TO_ARM_MODE(flash);
+  asm volatile(
+      ".code  32              \n"
+      "FLASH_ARM:             \n"
+      "MRS %0, CPSR           \n"
+      "BIC %0, %0, #0xC0      \n"
+      /* enable the irq*/ 
+      "MSR    CPSR_c, %0      \n"
+      "ORR    %0, %0, #0xc0   \n"
+      "MSR    CPSR_c, %0      \n"
+      "BX     R14             \n"
+      ".code  16              \n"
+      :"=&r"(reg) : "r" (_level)
+  );
+}
 
 /*
  *  Map interrupt level in task mode onto the hardware that the CPU
@@ -137,20 +143,20 @@ void _CPU_ISR_Flash_Thumb(int _level )
  *  ARM/Thumb dont distinguishd the interrupt levels
  */
 
-void _CPU_ISR_Set_level_Thumb(int  new_level )
-  {
-   int reg = 0; /* to avoid warning */		\
-   TO_ARM_MODE(SetISR);				\
-   asm volatile (\
-			".code	32			\n" \
-			"SET_LEVEL_ARM:		\n" \
-			"MRS  %0, CPSR		\n" \
-			"BIC  %0, %0, #0xC0 \n" \
-			"MSR  CPSR_c, %0 	\n" \
-			"BX   lr 			\n" \
-			".code	16 			\n" \
-			: "=r" (reg)		\
-			: "0" (reg));
+void _CPU_ISR_Set_level_Thumb(int new_level)
+{
+  int reg = 0; /* to avoid warning */
+  TO_ARM_MODE(SetISR);
+  asm volatile (\
+      ".code  32          \n" \
+      "SET_LEVEL_ARM:     \n" \
+      "MRS  %0, CPSR      \n" \
+      "BIC  %0, %0, #0xC0 \n" \
+      "MSR  CPSR_c, %0        \n" \
+      "BX   lr                        \n" \
+      ".code  16                      \n" \
+      : "=r" (reg)            \
+      : "0" (reg));
  }
 
 uint32_t  _CPU_ISR_Get_level_Thumb( void )
@@ -158,14 +164,14 @@ uint32_t  _CPU_ISR_Get_level_Thumb( void )
     uint32_t   reg = 0; /* to avoid warning */
     TO_ARM_MODE(GetISR); \
     asm volatile (\
-			".code	32 			\n"	\
-			"GET_ISR_ARM:		\n" \
-			"MRS  r0, cpsr 		\n" \
-			"AND  r0, r0, #0xC0 \n" \
-			"EOR	r0, r0, #0xC0 \n" \
-			"BX LR 				\n" \
-			".code	16			\n" \
-			".thumb_func		\n"  );
+                        ".code  32                      \n"     \
+                        "GET_ISR_ARM:           \n" \
+                        "MRS  r0, cpsr          \n" \
+                        "AND  r0, r0, #0xC0 \n" \
+                        "EOR    r0, r0, #0xC0 \n" \
+                        "BX LR                          \n" \
+                        ".code  16                      \n" \
+                        ".thumb_func            \n"  );
 }
 
 #endif