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authorSebastian Huber <sebastian.huber@embedded-brains.de>2018-01-31 08:02:21 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-01-31 08:03:30 +0100
commit9819425feecd8d06de1baaf8a8e07f7151623648 (patch)
treeffca1ab002784f0ae3c4b48f181f078fe426b4f9 /cpukit/score/cpu
parentAvoid Newlib-specific _EXFUN() (diff)
downloadrtems-9819425feecd8d06de1baaf8a8e07f7151623648.tar.bz2
epiphany: Fixes for GCC 7.3
GCC 7.3 defines __USER_LABEL_PREFIX__ to nothing.
Diffstat (limited to 'cpukit/score/cpu')
-rw-r--r--cpukit/score/cpu/epiphany/epiphany-context-switch.S5
-rw-r--r--cpukit/score/cpu/epiphany/epiphany-exception-handler.S20
2 files changed, 12 insertions, 13 deletions
diff --git a/cpukit/score/cpu/epiphany/epiphany-context-switch.S b/cpukit/score/cpu/epiphany/epiphany-context-switch.S
index 6d08389713..40744d1d11 100644
--- a/cpukit/score/cpu/epiphany/epiphany-context-switch.S
+++ b/cpukit/score/cpu/epiphany/epiphany-context-switch.S
@@ -39,7 +39,6 @@ PUBLIC(_CPU_Context_switch)
PUBLIC(_CPU_Context_restore)
PUBLIC(_CPU_Context_restore_fp)
PUBLIC(_CPU_Context_save_fp)
-PUBLIC(restore)
SYM(_CPU_Context_switch):
/* Disable interrupts and store all registers */
@@ -122,7 +121,7 @@ SYM(_CPU_Context_switch):
movfs r27, iret
str r27, [r0,66]
-SYM(restore):
+.Lrestore:
/* r1 contains buffer address, skip it */
ldr r2, [r1,2]
@@ -205,7 +204,7 @@ SYM(restore):
SYM(_CPU_Context_restore):
mov r1, r0
- b _restore
+ b .Lrestore
nop
/* No FP support for Epiphany yet */
diff --git a/cpukit/score/cpu/epiphany/epiphany-exception-handler.S b/cpukit/score/cpu/epiphany/epiphany-exception-handler.S
index 09c88fd861..23f0947cb4 100644
--- a/cpukit/score/cpu/epiphany/epiphany-exception-handler.S
+++ b/cpukit/score/cpu/epiphany/epiphany-exception-handler.S
@@ -43,12 +43,12 @@
EXTERN(bsp_start_vector_table_begin)
EXTERN(_Thread_Dispatch)
-PUBLIC(ISR_Handler)
+PUBLIC(_ISR_Handler)
.section .text, "ax"
.align 4
-TYPE_FUNC(ISR_Handler)
-SYM(ISR_Handler):
+TYPE_FUNC(_ISR_Handler)
+SYM(_ISR_Handler):
/* Reserve space for CPU_Exception_frame */
sub sp, sp, #(CPU_EXCEPTION_FRAME_SIZE)
@@ -134,8 +134,8 @@ SYM(ISR_Handler):
movfs r1,iret
str r1, [sp,64]
- mov r33, %low(__Per_CPU_Information)
- movt r33, %high(__Per_CPU_Information)
+ mov r33, %low(_Per_CPU_Information)
+ movt r33, %high(_Per_CPU_Information)
add r6, r33, #(PER_CPU_ISR_NEST_LEVEL)
add r8, r33, #(PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL)
@@ -151,7 +151,7 @@ SYM(ISR_Handler):
/* Keep sp (Exception frame address) in r32 - Callee saved */
mov r32, sp
- /* Keep __Per_CPU_Information address in r33 - Callee saved */
+ /* Keep _Per_CPU_Information address in r33 - Callee saved */
mov r33, r18
/* Call the exception handler from vector table.
@@ -163,7 +163,7 @@ SYM(ISR_Handler):
mov r27, r62
lsl r27, r27, #2
- mov r26, %low(_bsp_start_vector_table_begin)
+ mov r26, %low(bsp_start_vector_table_begin)
movt r15, #0
add r27, r27, r26
ldr r27, [r27]
@@ -184,7 +184,7 @@ jump_to_c_handler:
/* Switch back to the interrupted task stack */
mov sp, r32
- /* Get the address of __Per_CPU_Information */
+ /* Get the address of _Per_CPU_Information */
mov r18, r33
/* Decrement nesting level and enable multitasking */
@@ -213,8 +213,8 @@ jump_to_c_handler:
sub r35, r31, #0
beq exception_frame_restore
- mov r35, %low(__Thread_Dispatch)
- movt r35, %high(__Thread_Dispatch)
+ mov r35, %low(_Thread_Dispatch)
+ movt r35, %high(_Thread_Dispatch)
jalr r35
exception_frame_restore: