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authorAmaan Cheval <amaan.cheval@gmail.com>2018-08-13 16:03:12 +0530
committerJoel Sherrill <joel@rtems.org>2018-08-13 10:48:20 -0500
commit4544749e3c163c511a9a28992b3ac429515c0a5a (patch)
tree34043f7607ab3931634efa12da7b1f922cda4479 /cpukit/score/cpu/x86_64
parentbsps/x86_64: Reduce default RamSize to 1GiB (diff)
downloadrtems-4544749e3c163c511a9a28992b3ac429515c0a5a.tar.bz2
bsps/x86_64: Add paging support with 1GiB super pages
Updates #2898.
Diffstat (limited to 'cpukit/score/cpu/x86_64')
-rw-r--r--cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
index ac43a6366d..5d4b608eb8 100644
--- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h
@@ -45,6 +45,19 @@ RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val)
__asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) );
}
+
+RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment)
+{
+ __asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) );
+}
+
+RTEMS_INLINE_ROUTINE void cpuid(
+ uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx
+) {
+ __asm__ volatile ( "cpuid"
+ : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
+ : "a" (code) );
+}
#endif /* !ASM */
#endif