diff options
author | Amaan Cheval <amaan.cheval@gmail.com> | 2018-08-13 16:20:38 +0530 |
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committer | Joel Sherrill <joel@rtems.org> | 2018-08-13 10:48:20 -0500 |
commit | 686932125dd249a237bcb6d2f0ddb9f2ff1ce1b3 (patch) | |
tree | a83e550123771683c0bb6a77496abfe10729b36c /cpukit/score/cpu/x86_64/include | |
parent | bsps/x86_64: Add paging support with 1GiB super pages (diff) | |
download | rtems-686932125dd249a237bcb6d2f0ddb9f2ff1ce1b3.tar.bz2 |
bsps/x86_64: Add support for RTEMS interrupts
Updates #2898.
Diffstat (limited to 'cpukit/score/cpu/x86_64/include')
-rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpu.h | 107 | ||||
-rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h | 18 | ||||
-rw-r--r-- | cpukit/score/cpu/x86_64/include/rtems/score/idt.h | 131 |
3 files changed, 236 insertions, 20 deletions
diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h index 557d11109d..8f4a3c8d2e 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @@ -101,12 +101,57 @@ typedef struct { double some_float_register; } Context_Control_fp; +/* + * Caller-saved registers for interrupt frames + */ typedef struct { - uint32_t special_interrupt_register; + /** + * @note: rdi is a caller-saved register too, but it's used in function calls + * and is hence saved separately on the stack; + * + * @see DISTINCT_INTERRUPT_ENTRY + * @see _ISR_Handler + */ + + uint64_t rax; + uint64_t rcx; + uint64_t rdx; + uint64_t rsi; + uint64_t r8; + uint64_t r9; + uint64_t r10; + uint64_t r11; + + /* + * This holds the rsp just before _ISR_Handler is called; it's needed because + * in the handler, we align the stack to make further calls, and we're not + * sure how alignment may move the stack-pointer around, leaving no way to get + * back to the stack, and therefore the interrupt frame. + */ + uint64_t saved_rsp; + + /* XXX: + * - FS segment selector for TLS + * - x87 status word? + * - MMX? + * - XMM? + */ } CPU_Interrupt_frame; #endif /* !ASM */ +#define CPU_INTERRUPT_FRAME_SIZE 72 + +/* + * When SMP is enabled, percpuasm.c has a similar assert, but since we use the + * interrupt frame regardless of SMP, we'll confirm it here. + */ +#ifndef ASM + RTEMS_STATIC_ASSERT( + sizeof(CPU_Interrupt_frame) == CPU_INTERRUPT_FRAME_SIZE, + CPU_INTERRUPT_FRAME_SIZE + ); +#endif #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 @@ -126,31 +171,55 @@ typedef struct { #define _CPU_Initialize_vectors() -// XXX: For RTEMS critical sections -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - (_isr_cookie) = 0; /* do something to prevent warnings */ \ - } +#define _CPU_ISR_Enable(_level) \ +{ \ + amd64_enable_interrupts(); \ + _level = 0; \ + (void) _level; /* Prevent -Wunused-but-set-variable */ \ +} -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - (void) (_isr_cookie); /* prevent warnings from -Wunused-but-set-variable */ \ - } +#define _CPU_ISR_Disable(_level) \ +{ \ + amd64_enable_interrupts(); \ + _level = 1; \ + (void) _level; /* Prevent -Wunused-but-set-variable */ \ +} -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - } +#define _CPU_ISR_Flash(_level) \ +{ \ + amd64_enable_interrupts(); \ + amd64_disable_interrupts(); \ + _level = 1; \ + (void) _level; /* Prevent -Wunused-but-set-variable */ \ +} -RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled(uint32_t level) { - return false; + return (level & EFLAGS_INTR_ENABLE) != 0; } -#define _CPU_ISR_Set_level( new_level ) \ - { \ +RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) +{ + if ( new_level ) { + amd64_disable_interrupts(); } + else { + amd64_enable_interrupts(); + } +} + +RTEMS_INLINE_ROUTINE uint32_t _CPU_ISR_Get_level(void) +{ + uint64_t rflags; + + __asm__ volatile ( "pushf; \ + popq %0" + : "=rm" (rflags) + ); -uint32_t _CPU_ISR_Get_level( void ); + uint32_t level = (rflags & EFLAGS_INTR_ENABLE) ? 0 : 1; + return level; +} /* end of ISR handler macros */ @@ -228,8 +297,6 @@ void _CPU_ISR_install_vector( proc_ptr *old_handler ); -void _CPU_Install_interrupt_stack( void ); - void *_CPU_Thread_Idle_body( uintptr_t ignored ); void _CPU_Context_switch( diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h index 5d4b608eb8..09807f1489 100644 --- a/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h +++ b/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @@ -45,6 +45,14 @@ RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val) __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) ); } +RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) +{ + uint16_t segment = 0; + + __asm__ volatile ( "movw %%cs, %0" : "=r" (segment) : "0" (segment) ); + + return segment; +} RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment) { @@ -58,6 +66,16 @@ RTEMS_INLINE_ROUTINE void cpuid( : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) : "a" (code) ); } + +RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void) +{ + __asm__ volatile ( "sti" ); +} + +RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void) +{ + __asm__ volatile ( "cli" ); +} #endif /* !ASM */ #endif diff --git a/cpukit/score/cpu/x86_64/include/rtems/score/idt.h b/cpukit/score/cpu/x86_64/include/rtems/score/idt.h new file mode 100644 index 0000000000..e1f69b1409 --- /dev/null +++ b/cpukit/score/cpu/x86_64/include/rtems/score/idt.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2018. + * Amaan Cheval <amaan.cheval@gmail.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_IDT_H +#define _RTEMS_SCORE_IDT_H + +#include <rtems/score/basedefs.h> +#include <rtems/rtems/intr.h> + +#ifdef __cplusplus +extern "C" { +#endif + +#define IDT_INTERRUPT_GATE (0b1110) +#define IDT_PRESENT (0b10000000) + +/* + * XXX: The IDT size should be smaller given that we likely won't map all 256 + * vectors, but for simplicity, this works better. + */ +#define IDT_SIZE 256 + +/* Target vector number for spurious IRQs */ +#define BSP_VECTOR_SPURIOUS 0xFF +/* Target vector number for the APIC timer */ +#define BSP_VECTOR_APIC_TIMER 32 + +typedef struct _interrupt_descriptor { + uint16_t offset_0; // bits 0-15 + uint16_t segment_selector; // a segment selector in the GDT or LDT + /* bits 0-2 are the offset into the IST, stored in the TSS */ + uint8_t interrupt_stack_table; + uint8_t type_and_attributes; + uint16_t offset_1; // bits 16-31 + uint32_t offset_2; // bits 32-63 + uint32_t reserved_zero; +} interrupt_descriptor; + +extern interrupt_descriptor amd64_idt[IDT_SIZE]; + +struct idt_record { + uint16_t limit; /* Size of IDT array - 1 */ + uintptr_t base; /* Pointer to IDT array */ +} RTEMS_PACKED; + +RTEMS_STATIC_ASSERT( + sizeof(struct idt_record) == 10, + "IDT pointer must be exactly 10 bytes" +); + +void lidt(struct idt_record *idtr); + +interrupt_descriptor amd64_create_interrupt_descriptor( + uintptr_t handler, uint8_t types_and_attributes +); + +uintptr_t amd64_get_handler_from_idt(uint32_t vector); + +void amd64_install_raw_interrupt( + uint32_t vector, uintptr_t new_handler, uintptr_t *old_handler +); + +/* + * Called by _ISR_Handler to dispatch "RTEMS interrupts", i.e. call the + * registered RTEMS ISR. + */ +void amd64_dispatch_isr(rtems_vector_number vector); + +/* Defined in isr_handler.S */ +extern void rtems_irq_prologue_0(void); +extern void rtems_irq_prologue_1(void); +extern void rtems_irq_prologue_2(void); +extern void rtems_irq_prologue_3(void); +extern void rtems_irq_prologue_4(void); +extern void rtems_irq_prologue_5(void); +extern void rtems_irq_prologue_6(void); +extern void rtems_irq_prologue_7(void); +extern void rtems_irq_prologue_8(void); +extern void rtems_irq_prologue_9(void); +extern void rtems_irq_prologue_10(void); +extern void rtems_irq_prologue_11(void); +extern void rtems_irq_prologue_12(void); +extern void rtems_irq_prologue_13(void); +extern void rtems_irq_prologue_14(void); +extern void rtems_irq_prologue_15(void); +extern void rtems_irq_prologue_16(void); +extern void rtems_irq_prologue_17(void); +extern void rtems_irq_prologue_18(void); +extern void rtems_irq_prologue_19(void); +extern void rtems_irq_prologue_20(void); +extern void rtems_irq_prologue_21(void); +extern void rtems_irq_prologue_22(void); +extern void rtems_irq_prologue_23(void); +extern void rtems_irq_prologue_24(void); +extern void rtems_irq_prologue_25(void); +extern void rtems_irq_prologue_26(void); +extern void rtems_irq_prologue_27(void); +extern void rtems_irq_prologue_28(void); +extern void rtems_irq_prologue_29(void); +extern void rtems_irq_prologue_30(void); +extern void rtems_irq_prologue_31(void); +extern void rtems_irq_prologue_32(void); + +#ifdef __cplusplus +} +#endif + +#endif |