diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2014-05-20 17:45:07 +0200 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2014-10-06 13:19:18 +0200 |
| commit | 9bd7b3b1a26adc41678ec4d4a1d97f057cdb43a7 (patch) | |
| tree | e696df2a0aa20c45ac84c3d5de06a53731599495 /cpukit/score/cpu/sparc/rtems/score/cpu.h | |
| parent | SPARC: add BSP specific error handler (diff) | |
| download | rtems-9bd7b3b1a26adc41678ec4d4a1d97f057cdb43a7.tar.bz2 | |
SPARC: Fatal_halt use source and exit codes
The Fatal_halt handler now have two options, either halt
as before or enter system error state to return to
debugger or simulator. The exit-code is now also
propagated to the debugger which is very useful for
testing.
The CPU_Fatal_halt handler was split up into two, since
the only the LEON3 support the CPU power down.
The LEON3 halt now uses the power-down instruction to save
CPU power. This doesn't stop a potential watch-dog timer
from expiring.
Diffstat (limited to 'cpukit/score/cpu/sparc/rtems/score/cpu.h')
| -rw-r--r-- | cpukit/score/cpu/sparc/rtems/score/cpu.h | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 70d1785e54..6ce065cfe4 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -1080,14 +1080,8 @@ void _CPU_Context_Initialize( * location or a register, optionally disables interrupts, and * halts/stops the CPU. */ -#define _CPU_Fatal_halt( _source, _error ) \ - do { \ - uint32_t level; \ - \ - level = sparc_disable_interrupts(); \ - __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ - while (1); /* loop forever */ \ - } while (0) +extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) + RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; /* end of Fatal Error manager macros */ |