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authorSebastian Huber <sebastian.huber@embedded-brains.de>2016-11-10 15:17:28 +0100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2016-11-18 07:30:35 +0100
commit408609f6b9cd8e03d3886b7c150efbf7e59b5fb0 (patch)
tree0c4ec2f82334c0efb93f1222e4ee80a6ada166ce /cpukit/score/cpu/sparc/rtems/score/cpu.h
parentscore: Restrict task interrupt level to 0 on SMP (diff)
downloadrtems-408609f6b9cd8e03d3886b7c150efbf7e59b5fb0.tar.bz2
score: Add _ISR_Is_enabled()
In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates a level parameter and returns a boolean value. Update #2811.
Diffstat (limited to 'cpukit/score/cpu/sparc/rtems/score/cpu.h')
-rw-r--r--cpukit/score/cpu/sparc/rtems/score/cpu.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 27393b796e..07601de648 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -889,6 +889,14 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
+#define _CPU_ISR_Is_enabled( _isr_cookie ) \
+ sparc_interrupt_is_enabled( _isr_cookie )
+
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & SPARC_PSR_PIL_MASK ) == 0;
+}
+
/**
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not