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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-05 11:36:05 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-02-12 09:18:00 +0100 |
| commit | 97cf623d4ada641b0a59321f0e75a6b323ecf193 (patch) | |
| tree | 995ca3143804849f95c778e38c21c33cf2421faa /cpukit/score/cpu/sparc/cpu.c | |
| parent | bsps/sparc: Fix ambapp_find_by_idx() (diff) | |
| download | rtems-97cf623d4ada641b0a59321f0e75a6b323ecf193.tar.bz2 | |
sparc: Save/restore only non-volatile context
The _CPU_Context_switch() is a normal function call. The following
registers are volatile (the caller must assume that the register
contents are destroyed by the callee) according to "SYSTEM V APPLICATION
BINARY INTERFACE - SPARC Processor Supplement", Third Edition: g1, o0,
o1, o2, o3, o4, o5. Drop these registers from the context.
Ensure that offset defines match the structure offsets.
Diffstat (limited to 'cpukit/score/cpu/sparc/cpu.c')
| -rw-r--r-- | cpukit/score/cpu/sparc/cpu.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 11e31f9d10..3e08c26af7 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -29,6 +29,44 @@ RTEMS_STATIC_ASSERT( SPARC_PER_CPU_ISR_DISPATCH_DISABLE ); +#define SPARC_ASSERT_OFFSET(field, off) \ + RTEMS_STATIC_ASSERT( \ + offsetof(Context_Control, field) == off ## _OFFSET, \ + Context_Control_offset_ ## field \ + ) + +SPARC_ASSERT_OFFSET(g2_g3, G2); +SPARC_ASSERT_OFFSET(g4, G4); +SPARC_ASSERT_OFFSET(g5, G5); +SPARC_ASSERT_OFFSET(g6, G6); +SPARC_ASSERT_OFFSET(g7, G7); +SPARC_ASSERT_OFFSET(l0, L0); +SPARC_ASSERT_OFFSET(l1, L1); +SPARC_ASSERT_OFFSET(l2, L2); +SPARC_ASSERT_OFFSET(l3, L3); +SPARC_ASSERT_OFFSET(l4, L4); +SPARC_ASSERT_OFFSET(l5, L5); +SPARC_ASSERT_OFFSET(l6, L6); +SPARC_ASSERT_OFFSET(l7, L7); +SPARC_ASSERT_OFFSET(i0, I0); +SPARC_ASSERT_OFFSET(i1, I1); +SPARC_ASSERT_OFFSET(i2, I2); +SPARC_ASSERT_OFFSET(i3, I3); +SPARC_ASSERT_OFFSET(i4, I4); +SPARC_ASSERT_OFFSET(i5, I5); +SPARC_ASSERT_OFFSET(i6_fp, I6_FP); +SPARC_ASSERT_OFFSET(i7, I7); +SPARC_ASSERT_OFFSET(o6_sp, O6_SP); +SPARC_ASSERT_OFFSET(o7, O7); +SPARC_ASSERT_OFFSET(psr, PSR); +SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); + +RTEMS_STATIC_ASSERT( + (offsetof(Context_Control, g2_g3) + + offsetof(Context_Control, g4)) / 2 == G3_OFFSET, + Context_Control_offset_G3 +); + /* * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible |