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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-27 08:54:13 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:37 +0200 |
| commit | b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684 (patch) | |
| tree | 70654e29a9a7af7995aa6325e42ce36de176bccf /cpukit/score/cpu/riscv/riscv-context-switch.S | |
| parent | riscv: Remove x8 initialization (diff) | |
| download | rtems-b706b4a3c09184b2f8ebf5290dc2b1d4a4db6684.tar.bz2 | |
riscv: Remove mstatus from thread context
The mstatus register contains no thread-specific state which must be
saved/restored during a context switch. Machine interrupts (MIE) must
be enabled during a context switch.
Create separate CPU_Interrupt_frame structure.
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 54adc6d0b6..b6de9e6f2b 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -45,12 +45,6 @@ SYM(_CPU_Context_switch): GET_SELF_CPU_CONTROL a2 lw a3, PER_CPU_ISR_DISPATCH_DISABLE(a2) - /* Disable interrupts and store all registers */ - csrr t0, mstatus - SREG t0, (32 * CPU_SIZEOF_POINTER)(a0) - - csrci mstatus, RISCV_MSTATUS_MIE - SREG x1, (1 * CPU_SIZEOF_POINTER)(a0) SREG x2, (2 * CPU_SIZEOF_POINTER)(a0) SREG x4, (4 * CPU_SIZEOF_POINTER)(a0) @@ -119,12 +113,6 @@ SYM(_CPU_Context_switch): LREG x29, (29 * CPU_SIZEOF_POINTER)(a1) LREG x30, (30 * CPU_SIZEOF_POINTER)(a1) - /* Load mstatus */ - LREG x31, (32 * CPU_SIZEOF_POINTER)(a1) - csrw mstatus, x31 - - LREG x30, (30 * CPU_SIZEOF_POINTER)(a1) - LREG x11, (11 * CPU_SIZEOF_POINTER)(a1) ret |