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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 08:20:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:38 +0200 |
| commit | 694e79a0b778e20b70c04e024ec43e76e563cc61 (patch) | |
| tree | ef15a5d64d3a2484f8f917c2835c9e7c4f5ef7e8 /cpukit/score/cpu/riscv/riscv-context-switch.S | |
| parent | riscv: Remove dead code (diff) | |
| download | rtems-694e79a0b778e20b70c04e024ec43e76e563cc61.tar.bz2 | |
riscv: Add TLS support
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-context-switch.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S b/cpukit/score/cpu/riscv/riscv-context-switch.S index 1b82e2aa79..3626155409 100644 --- a/cpukit/score/cpu/riscv/riscv-context-switch.S +++ b/cpukit/score/cpu/riscv/riscv-context-switch.S @@ -67,6 +67,7 @@ SYM(_CPU_Context_switch): LREG ra, RISCV_CONTEXT_RA(a1) LREG sp, RISCV_CONTEXT_SP(a1) + LREG tp, RISCV_CONTEXT_TP(a1) LREG s0, RISCV_CONTEXT_S0(a1) LREG s1, RISCV_CONTEXT_S1(a1) LREG s2, RISCV_CONTEXT_S2(a1) |