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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-02 15:21:36 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-02 15:21:36 +0200 |
| commit | e07b51a71010ca67dc3f5c18c66756db34e18915 (patch) | |
| tree | afb46a2f568e2548c32176136978f9257a0df3d9 /cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | |
| parent | score: Increase PER_CPU_CONTROL_SIZE_APPROX (diff) | |
| download | rtems-e07b51a71010ca67dc3f5c18c66756db34e18915.tar.bz2 | |
riscv: Fix fcsr initialization
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 2bff71567c..9c50be89dd 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -286,6 +286,15 @@ typedef struct { uintptr_t a1; } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; +static inline uint32_t _RISCV_Read_FCSR( void ) +{ + uint32_t fcsr; + + __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) ); + + return fcsr; +} + #ifdef RTEMS_SMP static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) |