From e07b51a71010ca67dc3f5c18c66756db34e18915 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 2 Jul 2018 15:21:36 +0200 Subject: riscv: Fix fcsr initialization Update #3433. --- cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h') diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h index 2bff71567c..9c50be89dd 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h @@ -286,6 +286,15 @@ typedef struct { uintptr_t a1; } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame; +static inline uint32_t _RISCV_Read_FCSR( void ) +{ + uint32_t fcsr; + + __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) ); + + return fcsr; +} + #ifdef RTEMS_SMP static inline struct Per_CPU_Control *_RISCV_Get_current_per_CPU_control( void ) -- cgit v1.2.3