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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 10:15:53 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
| commit | 5694b0cce4908172af3f6292e7f111ac26620af7 (patch) | |
| tree | f351a0f6094538b59382ef037389f5884ed81926 /cpukit/score/cpu/riscv/cpu.c | |
| parent | riscv: Add exception codes (diff) | |
| download | rtems-5694b0cce4908172af3f6292e7f111ac26620af7.tar.bz2 | |
riscv: New CPU_Exception_frame
Use the CPU_Interrupt_frame for the volatile context. Add non-volatile
registers and extra state on top of it.
Update #3433.
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 687502f705..6b29de2273 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -130,6 +130,44 @@ RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 ); #endif /* __riscv_flen */ +#define RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( field, off ) \ + RTEMS_STATIC_ASSERT( \ + offsetof( CPU_Exception_frame, field) == RISCV_EXCEPTION_FRAME_ ## off, \ + riscv_context_offset_ ## field \ + ) + +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( mcause, MCAUSE ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( sp, SP ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( gp, GP ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( tp, TP ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s2, S2 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s3, S3 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s4, S4 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s5, S5 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s6, S6 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s7, S7 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s8, S8 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s9, S9 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s10, S10 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( s11, S11 ); + +#if __riscv_flen > 0 + +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs0, FS0 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs1, FS1 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs2, FS2 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs3, FS3 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs4, FS4 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs5, FS5 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs6, FS6 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs7, FS7 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs8, FS8 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs9, FS9 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs10, FS10 ); +RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( fs11, FS11 ); + +#endif /* __riscv_flen */ + RTEMS_STATIC_ASSERT( sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, riscv_interrupt_frame_size |