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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-28 09:32:26 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-06-29 10:04:38 +0200 |
commit | 52352387cc0b502fd42164604ae9217700b83e31 (patch) | |
tree | 310ce36df9400a55d09b11f87a9cb5bb0460584c /cpukit/score/cpu/riscv/cpu.c | |
parent | riscv: Fix global construction (diff) | |
download | rtems-52352387cc0b502fd42164604ae9217700b83e31.tar.bz2 |
riscv: Add floating-point support
Update #3433.
Diffstat (limited to '')
-rw-r--r-- | cpukit/score/cpu/riscv/cpu.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 508f0c83b2..687502f705 100644 --- a/cpukit/score/cpu/riscv/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -59,6 +59,24 @@ RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 ); RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 ); RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 ); +#if __riscv_flen > 0 + +RISCV_ASSERT_CONTEXT_OFFSET( fcsr, FCSR ); +RISCV_ASSERT_CONTEXT_OFFSET( fs0, FS0 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs1, FS1 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs2, FS2 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs3, FS3 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs4, FS4 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs5, FS5 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs6, FS6 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs7, FS7 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs8, FS8 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs9, FS9 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs10, FS10 ); +RISCV_ASSERT_CONTEXT_OFFSET( fs11, FS11 ); + +#endif /* __riscv_flen */ + #define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \ RTEMS_STATIC_ASSERT( \ offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \ @@ -86,6 +104,32 @@ RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 ); RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 ); RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 ); +#if __riscv_flen > 0 + +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fcsr, FCSR ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft0, FT0 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft1, FT1 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft2, FT2 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft3, FT3 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft4, FT4 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft5, FT5 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft6, FT6 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft7, FT7 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft8, FT8 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft9, FT9 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft10, FT10 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ft11, FT11 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa0, FA0 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa1, FA1 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa2, FA2 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa3, FA3 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa4, FA4 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa5, FA5 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa6, FA6 ); +RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 ); + +#endif /* __riscv_flen */ + RTEMS_STATIC_ASSERT( sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0, riscv_interrupt_frame_size |