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| author | Hesham Almatary <heshamelmatary@gmail.com> | 2017-10-27 15:18:40 +1100 |
|---|---|---|
| committer | Hesham Almatary <heshamelmatary@gmail.com> | 2017-11-01 10:10:27 +1100 |
| commit | 11ff3a9e72ca261a6024b16c34c6fb35054fd53a (patch) | |
| tree | ffddc78ce5f3ceff414fa7551f49c7ccb5510672 /cpukit/score/cpu/riscv/cpu.c | |
| parent | testsuite: Add bspIo for a local printk. (diff) | |
| download | rtems-11ff3a9e72ca261a6024b16c34c6fb35054fd53a.tar.bz2 | |
cpukit: RISC-V - make riscv32 code work for riscv64 - v2
* Use #ifdefs for 32/64 bit code
* Use unsigned long which is 32-bit on riscv32 and 64-bit on riscv64 (register size)
* Move the code to a new shared riscv folder to be shared between riscv32 and riscv64
* Rename RTEMS_CPU extracted from command line to shared riscv target s/riscv*/riscv
Update #3109
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/riscv/cpu.c (renamed from cpukit/score/cpu/riscv32/cpu.c) | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpukit/score/cpu/riscv32/cpu.c b/cpukit/score/cpu/riscv/cpu.c index 7061d10024..8d2926e715 100644 --- a/cpukit/score/cpu/riscv32/cpu.c +++ b/cpukit/score/cpu/riscv/cpu.c @@ -1,5 +1,5 @@ /* - * riscv32 CPU Dependent Source + * RISC-V CPU Dependent Source * * Copyright (c) 2015 University of York. * Hesham ALmatary <hesham@alumni.york.ac.uk> @@ -59,12 +59,12 @@ void _CPU_Initialize(void) /* Do nothing */ } -void _CPU_ISR_Set_level(uint32_t level) +void _CPU_ISR_Set_level(unsigned long level) { /* Do nothing */ } -uint32_t _CPU_ISR_Get_level( void ) +unsigned long _CPU_ISR_Get_level( void ) { /* Do nothing */ return 0; @@ -80,7 +80,7 @@ void _CPU_ISR_install_raw_handler( } void _CPU_ISR_install_vector( - uint32_t vector, + unsigned long vector, proc_ptr new_handler, proc_ptr *old_handler ) |