diff options
| author | Till Straumann <strauman@slac.stanford.edu> | 2007-12-07 21:24:33 +0000 |
|---|---|---|
| committer | Till Straumann <strauman@slac.stanford.edu> | 2007-12-07 21:24:33 +0000 |
| commit | aeca15c87bb141fae458ba8aad617a722685f4ad (patch) | |
| tree | b992e5b30f02e592a1b6c5900e289b0134350642 /cpukit/score/cpu/powerpc | |
| parent | 2007-12-07 Till Straumann <strauman@slac.stanford.edu> (diff) | |
| download | rtems-aeca15c87bb141fae458ba8aad617a722685f4ad.tar.bz2 | |
2007-12-03 Till Straumann <strauman@slac.stanford.edu>
* rtems/powerpc/registers.h: added definitions for MSR_CE,
MSR_DE (bookE).
Diffstat (limited to 'cpukit/score/cpu/powerpc')
| -rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 5 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index 0691a48487..965594934c 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2007-12-03 Till Straumann <strauman@slac.stanford.edu> + + * rtems/powerpc/registers.h: added definitions for MSR_CE, + MSR_DE (bookE). + 2007-12-06 Joel Sherrill <joel.sherrill@OARcorp.com> * rtems/old-exceptions/cpu.h: Remove extra ifndef. diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h index 2033f79c53..527b610fec 100644 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @@ -26,6 +26,7 @@ extern "C" { #define MSR_VE (1<<25) /* Alti-Vec enable (7400+) */ #define MSR_POW (1<<18) /* Enable Power Management */ #define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* BookE critical interrupt */ #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */ #define MSR_EE (1<<15) /* External Interrupt enable */ #define MSR_PR (1<<14) /* Supervisor/User privilege */ @@ -34,6 +35,7 @@ extern "C" { #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ #define MSR_SE (1<<10) /* Single Step */ #define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* BookE debug exception */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ #define MSR_IR (1<<5) /* Instruction MMU enable */ |