(PPC_Get_timebase_register, PPC_Set_timebase_register): New.

1 files changed, 37 insertions, 0 deletions

diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index 25ad5d627e..23fd4a3906 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -160,5 +160,42 @@ static inline uint32_t CPU_swap_u32(
 
 #endif /* ASM */
 
+#ifndef ASM
+/*
+ *  Routines to access the time base register
+ */
+
+static inline uint64_t PPC_Get_timebase_register( void )
+{
+  uint32_t tbr_low;
+  uint32_t tbr_high;
+  uint32_t tbr_high_old;
+  uint64_t tbr;
+
+  do {
+    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
+    asm volatile( "mftb  %0" : "=r" (tbr_low));
+    asm volatile( "mftbu %0" : "=r" (tbr_high));
+  } while ( tbr_high_old != tbr_high );
+
+  tbr = tbr_high;
+  tbr <<= 32;
+  tbr |= tbr_low;
+  return tbr;
+}
+
+static inline  void PPC_Set_timebase_register (uint64_t tbr)
+{
+  uint32_t tbr_low;
+  uint32_t tbr_high;
+
+  tbr_low = (tbr & 0xffffffff) ;
+  tbr_high = (tbr >> 32) & 0xffffffff;
+  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
+  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
+  
+}
+#endif /* ASM */
+
 #endif /* _RTEMS_SCORE_CPU_H */