diff options
author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-08-01 10:57:46 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-08-22 16:26:19 +0200 |
commit | a6f84b275318dbd89ba0bfd12ff6df631a8ac4bc (patch) | |
tree | 0105282863a5a9b538098ed88a5bd72ab799aa9c /cpukit/score/cpu/powerpc/rtems | |
parent | powerpc: 64-bit _CPU_Context_Initialize() support (diff) | |
download | rtems-a6f84b275318dbd89ba0bfd12ff6df631a8ac4bc.tar.bz2 |
powerpc: Add 64-bit context/interrupt support
Update #3082.
Diffstat (limited to 'cpukit/score/cpu/powerpc/rtems')
-rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpu.h | 75 | ||||
-rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 152 | ||||
-rw-r--r-- | cpukit/score/cpu/powerpc/rtems/score/powerpc.h | 6 |
3 files changed, 143 insertions, 90 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h index 72fc48318f..cacd3ea105 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h @@ -25,7 +25,7 @@ * * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). * - * Copyright (c) 2010, 2016 embedded brains GmbH. + * Copyright (c) 2010, 2017 embedded brains GmbH. * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -181,10 +181,16 @@ extern "C" { */ #ifndef __SPE__ - #define PPC_GPR_TYPE uint32_t - #define PPC_GPR_SIZE 4 - #define PPC_GPR_LOAD lwz - #define PPC_GPR_STORE stw + #define PPC_GPR_TYPE uintptr_t + #if defined(__powerpc64__) + #define PPC_GPR_SIZE 8 + #define PPC_GPR_LOAD ld + #define PPC_GPR_STORE std + #else + #define PPC_GPR_SIZE 4 + #define PPC_GPR_LOAD lwz + #define PPC_GPR_STORE stw + #endif #else #define PPC_GPR_TYPE uint64_t #define PPC_GPR_SIZE 8 @@ -192,6 +198,20 @@ extern "C" { #define PPC_GPR_STORE evstdd #endif +#if defined(__powerpc64__) + #define PPC_REG_SIZE 8 + #define PPC_REG_LOAD ld + #define PPC_REG_STORE std + #define PPC_REG_STORE_UPDATE stdu + #define PPC_REG_CMP cmpd +#else + #define PPC_REG_SIZE 4 + #define PPC_REG_LOAD lwz + #define PPC_REG_STORE stw + #define PPC_REG_STORE_UPDATE stwu + #define PPC_REG_CMP cmpw +#endif + #ifndef ASM /* @@ -200,10 +220,10 @@ extern "C" { * Linux and Embedded") */ typedef struct { - uint32_t gpr1; uint32_t msr; - uint32_t lr; uint32_t cr; + uintptr_t gpr1; + uintptr_t lr; PPC_GPR_TYPE gpr14; PPC_GPR_TYPE gpr15; PPC_GPR_TYPE gpr16; @@ -275,7 +295,7 @@ typedef struct { * the previous items to optimize the context switch. We must not set the * following items to zero via the dcbz. */ - uint32_t gpr2; + uintptr_t tp; #if defined(RTEMS_SMP) volatile uint32_t is_executing; #endif @@ -322,13 +342,14 @@ static inline ppc_context *ppc_get_context( const Context_Control *context ) #endif #endif /* ASM */ -#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) -#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) -#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) -#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) +#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) +#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) +#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) +#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ - (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) + (((gpr) - 14) * PPC_GPR_SIZE + \ + PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) @@ -352,7 +373,7 @@ static inline ppc_context *ppc_get_context( const Context_Control *context ) #ifdef PPC_MULTILIB_ALTIVEC #define PPC_CONTEXT_OFFSET_V( v ) \ - ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) + ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) @@ -367,10 +388,10 @@ static inline ppc_context *ppc_get_context( const Context_Control *context ) #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) + ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) #else #define PPC_CONTEXT_OFFSET_F( f ) \ - ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) + ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) #endif #ifdef PPC_MULTILIB_FPU @@ -406,10 +427,11 @@ static inline ppc_context *ppc_get_context( const Context_Control *context ) #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) #endif -#define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_VOLATILE_SIZE +#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE #ifdef RTEMS_SMP - #define PPC_CONTEXT_OFFSET_IS_EXECUTING (PPC_CONTEXT_VOLATILE_SIZE + 4) + #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ + (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) #endif #ifndef ASM @@ -1056,13 +1078,15 @@ void _CPU_Context_validate( uintptr_t pattern ); #endif typedef struct { - uint32_t EXC_SRR0; - uint32_t EXC_SRR1; + uintptr_t EXC_SRR0; + uintptr_t EXC_SRR1; uint32_t _EXC_number; + uint32_t RESERVED_FOR_ALIGNMENT_0; uint32_t EXC_CR; - uint32_t EXC_CTR; uint32_t EXC_XER; - uint32_t EXC_LR; + uintptr_t EXC_CTR; + uintptr_t EXC_LR; + uintptr_t RESERVED_FOR_ALIGNMENT_1; #ifdef __SPE__ uint32_t EXC_SPEFSCR; uint64_t EXC_ACC; @@ -1099,13 +1123,13 @@ typedef struct { PPC_GPR_TYPE GPR29; PPC_GPR_TYPE GPR30; PPC_GPR_TYPE GPR31; - #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) - uint32_t reserved_for_alignment; - #endif + uintptr_t RESERVED_FOR_ALIGNMENT_2; #ifdef PPC_MULTILIB_ALTIVEC uint32_t VRSAVE; + uint32_t RESERVED_FOR_ALIGNMENT_3[3]; /* This field must take stvewx/lvewx requirements into account */ + uint32_t RESERVED_FOR_ALIGNMENT_4[3]; uint32_t VSCR; uint8_t V0[16]; @@ -1175,6 +1199,7 @@ typedef struct { double F30; double F31; uint64_t FPSCR; + uint64_t RESERVED_FOR_ALIGNMENT_5; #endif } CPU_Exception_frame; diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h index 57c2db1822..c292feb6fd 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h @@ -10,7 +10,7 @@ * * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu> * - * Copyright (c) 2009, 2016 embedded brains GmbH + * Copyright (c) 2009, 2017 embedded brains GmbH * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -22,13 +22,71 @@ #include <rtems/score/cpu.h> -#define SRR0_FRAME_OFFSET 8 -#define SRR1_FRAME_OFFSET 12 -#define EXCEPTION_NUMBER_OFFSET 16 -#define EXC_CR_OFFSET 20 -#define EXC_CTR_OFFSET 24 -#define EXC_XER_OFFSET 28 -#define EXC_LR_OFFSET 32 +/* Exception stack frame -> BSP_Exception_frame */ +#ifdef __powerpc64__ + #define FRAME_LINK_SPACE 32 +#else + #define FRAME_LINK_SPACE 8 +#endif + +#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE +#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE) +#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE) +#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4) +#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8) +#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4) +#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4) +#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE) +#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE) + +#ifndef __SPE__ + #define PPC_EXC_GPR_OFFSET(gpr) \ + ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) + #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4) + #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) + #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) + #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) + #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) + #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32)) + #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) + #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) + #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) + #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) + #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20)) + #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) + #elif defined(PPC_MULTILIB_ALTIVEC) + #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) + #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) + #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4) + #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32) + #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12) + #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE) + #elif defined(PPC_MULTILIB_FPU) + #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33)) + #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32) + #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34) + #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13)) + #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE) + #else + #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33) + #define CPU_INTERRUPT_FRAME_SIZE \ + (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE) + #endif +#else + #define PPC_EXC_SPEFSCR_OFFSET 44 + #define PPC_EXC_ACC_OFFSET 48 + #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) + #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4) + #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) + #define PPC_EXC_FRAME_SIZE 320 +#endif + #define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0) #define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1) #define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2) @@ -62,52 +120,6 @@ #define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30) #define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31) -/* Exception stack frame -> BSP_Exception_frame */ -#define FRAME_LINK_SPACE 8 - -#ifndef __SPE__ - #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 36) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4) - #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) - #define PPC_EXC_VRSAVE_OFFSET 168 - #define PPC_EXC_VSCR_OFFSET 172 - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 688) - #define PPC_EXC_FPSCR_OFFSET 944 - #define PPC_EXC_FRAME_SIZE 960 - #define PPC_EXC_MIN_VSCR_OFFSET 92 - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96) - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 416) - #define PPC_EXC_MIN_FPSCR_OFFSET 528 - #define CPU_INTERRUPT_FRAME_SIZE 544 - #elif defined(PPC_MULTILIB_ALTIVEC) - #define PPC_EXC_VRSAVE_OFFSET 168 - #define PPC_EXC_VSCR_OFFSET 172 - #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + 176) - #define PPC_EXC_FRAME_SIZE 688 - #define PPC_EXC_MIN_VSCR_OFFSET 92 - #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + 96) - #define CPU_INTERRUPT_FRAME_SIZE 416 - #elif defined(PPC_MULTILIB_FPU) - #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + 168) - #define PPC_EXC_FPSCR_OFFSET 424 - #define PPC_EXC_FRAME_SIZE 448 - #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + 96) - #define PPC_EXC_MIN_FPSCR_OFFSET 92 - #define CPU_INTERRUPT_FRAME_SIZE 224 - #else - #define PPC_EXC_FRAME_SIZE 176 - #define CPU_INTERRUPT_FRAME_SIZE 96 - #endif -#else - #define PPC_EXC_SPEFSCR_OFFSET 36 - #define PPC_EXC_ACC_OFFSET 40 - #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 48) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4) - #define CPU_INTERRUPT_FRAME_SIZE 160 - #define PPC_EXC_FRAME_SIZE 320 -#endif - #define CPU_PER_CPU_CONTROL_SIZE 0 #ifdef RTEMS_SMP @@ -124,15 +136,24 @@ extern "C" { #endif typedef struct { - uint32_t FRAME_SP; - uint32_t FRAME_LR; - uint32_t EXC_SRR0; - uint32_t EXC_SRR1; - uint32_t unused; + uintptr_t FRAME_SP; + #ifdef __powerpc64__ + uint32_t FRAME_CR; + uint32_t FRAME_RESERVED; + #endif + uintptr_t FRAME_LR; + #ifdef __powerpc64__ + uintptr_t FRAME_TOC; + #endif + uintptr_t EXC_SRR0; + uintptr_t EXC_SRR1; + uint32_t RESERVED_FOR_ALIGNMENT_0; + uint32_t EXC_INTERRUPT_ENTRY_INSTANT; uint32_t EXC_CR; - uint32_t EXC_CTR; uint32_t EXC_XER; - uint32_t EXC_LR; + uintptr_t EXC_CTR; + uintptr_t EXC_LR; + uintptr_t EXC_INTERRUPT_FRAME; #ifdef __SPE__ uint32_t EXC_SPEFSCR; uint64_t EXC_ACC; @@ -150,12 +171,12 @@ typedef struct { PPC_GPR_TYPE GPR10; PPC_GPR_TYPE GPR11; PPC_GPR_TYPE GPR12; - uint32_t EARLY_INSTANT; #ifdef PPC_MULTILIB_ALTIVEC /* This field must take stvewx/lvewx requirements into account */ + uint32_t RESERVED_FOR_ALIGNMENT_3[3]; uint32_t VSCR; - uint8_t V0[16] RTEMS_ALIGNED(16); + uint8_t V0[16]; uint8_t V1[16]; uint8_t V2[16]; uint8_t V3[16]; @@ -192,9 +213,10 @@ typedef struct { double F12; double F13; uint64_t FPSCR; + uint64_t RESERVED_FOR_ALIGNMENT_4; #endif - #if !defined(PPC_MULTILIB_ALTIVEC) && !defined(PPC_MULTILIB_FPU) - uint32_t RESERVED_FOR_STACK_ALIGNMENT; + #if PPC_STACK_RED_ZONE_SIZE > 0 + uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ]; #endif } CPU_Interrupt_frame; diff --git a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h index 29469bc584..88ee0020e6 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h +++ b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h @@ -140,6 +140,12 @@ extern "C" { #define PPC_ALIGNMENT 8 #endif +#ifdef __powerpc64__ +#define PPC_STACK_RED_ZONE_SIZE 512 +#else +#define PPC_STACK_RED_ZONE_SIZE 0 +#endif + /* * Unless specified above, If the model has FP support, it is assumed to * support doubles (8-byte floating point numbers). |