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authorJoel Sherrill <joel.sherrill@oarcorp.com>2012-06-11 13:00:57 -0500
committerJoel Sherrill <joel.sherrill@oarcorp.com>2012-06-11 13:00:57 -0500
commit9da42fb87a077bd19df24224c66799ddf4925026 (patch)
treef4d9f76f4544f28464781ec6d146b4e484bfacd6 /cpukit/score/cpu/powerpc/rtems/score/cpu.h
parentmips/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Initialize (diff)
downloadrtems-9da42fb87a077bd19df24224c66799ddf4925026.tar.bz2
powerpc/cpu.h: Define CPU_SIMPLE_VECTORED_INTERRUPTS and remove _CPU_ISR_Initialize
Diffstat (limited to 'cpukit/score/cpu/powerpc/rtems/score/cpu.h')
-rw-r--r--cpukit/score/cpu/powerpc/rtems/score/cpu.h16
1 files changed, 14 insertions, 2 deletions
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index e845362266..840df7a5b0 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -405,6 +405,20 @@ typedef struct CPU_Interrupt_frame {
#endif /* ASM */
/*
+ * Does the CPU follow the simple vectored interrupt model?
+ *
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
+ *
+ * PowerPC Specific Information:
+ *
+ * The PowerPC and x86 were the first to use the PIC interrupt model.
+ * They do not use the simple vectored interrupt model.
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
+
+/*
* Does RTEMS manage a dedicated interrupt stack in software?
*
* If TRUE, then a stack is allocated in _ISR_Handler_initialization.
@@ -593,8 +607,6 @@ SCORE_EXTERN struct {
* ISR handler macros
*/
-#define _CPU_Initialize_vectors()
-
/*
* Disable all interrupts for an RTEMS critical section. The previous
* level is returned in _isr_cookie.