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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-11-02 13:02:20 +0100 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-09-08 15:54:23 +0200 |
commit | d907c2294a438f07099730b88ff88a659e940de7 (patch) | |
tree | 152a6878727e1699624a34759bc465a54172182e /cpukit/score/cpu/powerpc/cpu.c | |
parent | rtems: Include <rtems/score/cpuopts.h> (diff) | |
download | rtems-d907c2294a438f07099730b88ff88a659e940de7.tar.bz2 |
powerpc: Add support for VRSAVE
The VRSAVE feature of the Altivec unit can be used to reduce the amount of
Altivec registers which need to be saved/restored during interrupt processing
and context switches.
In order to use the VRSAVE optimization a corresponding multilib (-mvrsave) is
required, see GCC configuration. The -mvrsave option must be added to the
ABI_FLAGS of the BSP.
Currently only the -mcpu=e6500 based QorIQ BSP support this optimization.
Update #4712.
Diffstat (limited to 'cpukit/score/cpu/powerpc/cpu.c')
-rw-r--r-- | cpukit/score/cpu/powerpc/cpu.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/cpukit/score/cpu/powerpc/cpu.c b/cpukit/score/cpu/powerpc/cpu.c index 6147d7be74..bdb9cf6ab5 100644 --- a/cpukit/score/cpu/powerpc/cpu.c +++ b/cpukit/score/cpu/powerpc/cpu.c @@ -79,8 +79,10 @@ PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE); #endif #ifdef PPC_MULTILIB_ALTIVEC + PPC_ASSERT_OFFSET(vrsave, VRSAVE); + PPC_ASSERT_OFFSET(vscr, VSCR); RTEMS_STATIC_ASSERT( - PPC_CONTEXT_OFFSET_V20 % 16 == 0, + PPC_CONTEXT_OFFSET_V20 % PPC_DEFAULT_CACHE_LINE_SIZE == 0, ppc_context_altivec ); PPC_ASSERT_OFFSET(v20, V20); @@ -95,7 +97,6 @@ PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE); PPC_ASSERT_OFFSET(v29, V29); PPC_ASSERT_OFFSET(v30, V30); PPC_ASSERT_OFFSET(v31, V31); - PPC_ASSERT_OFFSET(vrsave, VRSAVE); #endif #ifdef PPC_MULTILIB_FPU |