Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

8 files changed, 0 insertions, 1191 deletions

diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h
deleted file mode 100644
index a3f2f03d36..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/cpu.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/**
- * @file
- *
- * @brief Altera Nios II CPU Department Source
- */
-
-/*
- *  Copyright (c) 2011 embedded brains GmbH
- *
- *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
- *
- *  COPYRIGHT (c) 1989-2004.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPU_H
-#define _RTEMS_SCORE_CPU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/types.h>
-#include <rtems/score/nios2.h>
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
-
-#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
-
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-#define CPU_ISR_PASSES_FRAME_POINTER FALSE
-
-#define CPU_HARDWARE_FP FALSE
-
-#define CPU_SOFTWARE_FP FALSE
-
-#define CPU_CONTEXT_FP_SIZE 0
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-#define CPU_USE_DEFERRED_FP_SWITCH FALSE
-
-#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
-
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-
-#define CPU_STACK_GROWS_UP FALSE
-
-/* FIXME: Is this the right value? */
-#define CPU_CACHE_LINE_BYTES 32
-
-#define CPU_STRUCTURE_ALIGNMENT \
-  RTEMS_SECTION( ".sdata" ) RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
-
-#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
-
-#define CPU_SIZEOF_POINTER 4
-
-/*
- * Alignment value according to "Nios II Processor Reference" chapter 7
- * "Application Binary Interface" section "Memory Alignment".
- */
-#define CPU_ALIGNMENT 4
-
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * Alignment value according to "Nios II Processor Reference" chapter 7
- * "Application Binary Interface" section "Stacks".
- */
-#define CPU_STACK_ALIGNMENT 4
-
-/*
- * A Nios II configuration with an external interrupt controller (EIC) supports
- * up to 64 interrupt levels.  A Nios II configuration with an internal
- * interrupt controller (IIC) has only two interrupt levels (enabled and
- * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
- * take care about configuration specific mappings.
- */
-#define CPU_MODES_INTERRUPT_MASK 0x3f
-
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-
-#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
-
-#define CPU_MAXIMUM_PROCESSORS 32
-
-#ifndef ASM
-
-/**
- * @brief Thread register context.
- *
- * The thread register context covers the non-volatile registers, the thread
- * stack pointer, the return address, and the processor status.
- *
- * There is no need to save the global pointer (gp) since it is a system wide
- * constant and set-up with the C runtime environment.
- *
- * The @a thread_dispatch_disabled field is used for the external interrupt
- * controller (EIC) support.
- *
- * @see _Nios2_Thread_dispatch_disabled
- */
-typedef struct {
-  uint32_t r16;
-  uint32_t r17;
-  uint32_t r18;
-  uint32_t r19;
-  uint32_t r20;
-  uint32_t r21;
-  uint32_t r22;
-  uint32_t r23;
-  uint32_t fp;
-  uint32_t status;
-  uint32_t sp;
-  uint32_t ra;
-  uint32_t thread_dispatch_disabled;
-  uint32_t stack_mpubase;
-  uint32_t stack_mpuacc;
-} Context_Control;
-
-#define _CPU_Context_Get_SP( _context ) \
-  (_context)->sp
-
-typedef void CPU_Interrupt_frame;
-
-typedef struct {
-  uint32_t r1;
-  uint32_t r2;
-  uint32_t r3;
-  uint32_t r4;
-  uint32_t r5;
-  uint32_t r6;
-  uint32_t r7;
-  uint32_t r8;
-  uint32_t r9;
-  uint32_t r10;
-  uint32_t r11;
-  uint32_t r12;
-  uint32_t r13;
-  uint32_t r14;
-  uint32_t r15;
-  uint32_t r16;
-  uint32_t r17;
-  uint32_t r18;
-  uint32_t r19;
-  uint32_t r20;
-  uint32_t r21;
-  uint32_t r22;
-  uint32_t r23;
-  uint32_t gp;
-  uint32_t fp;
-  uint32_t sp;
-  uint32_t ra;
-  uint32_t et;
-  uint32_t ea;
-  uint32_t status;
-  uint32_t ienable;
-  uint32_t ipending;
-} CPU_Exception_frame;
-
-#define _CPU_Initialize_vectors()
-
-/**
- * @brief Macro to disable interrupts.
- *
- * The processor status before disabling the interrupts will be stored in
- * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
- * _CPU_ISR_Enable().
- *
- * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
- * the status register representing the interrupt level.  The global symbol
- * _Nios2_ISR_Status_bits will be used to set the bits representing an
- * interrupt level that disables interrupts.  Both global symbols must be
- * provided by the board support package.
- *
- * In case the Nios II uses the internal interrupt controller (IIC), then only
- * the PIE status bit is used.
- *
- * In case the Nios II uses the external interrupt controller (EIC), then the
- * RSIE status bit or the IL status field is used depending on the interrupt
- * handling variant and the shadow register usage.
- */
-#define _CPU_ISR_Disable( _isr_cookie ) \
-  do { \
-    int _tmp; \
-    __asm__ volatile ( \
-      "rdctl %0, status\n" \
-      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
-      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
-      "and %1, %0, %1\n" \
-      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
-      "wrctl status, %1" \
-      : "=&r" (_isr_cookie), "=&r" (_tmp) \
-    ); \
-  } while ( 0 )
-
-/**
- * @brief Macro to restore the processor status.
- *
- * The @a _isr_cookie must contain the processor status returned by
- * _CPU_ISR_Disable().  The value is not modified.
- */
-#define _CPU_ISR_Enable( _isr_cookie ) \
-  __builtin_wrctl( 0, (int) _isr_cookie )
-
-/**
- * @brief Macro to restore the processor status and disable the interrupts
- * again.
- *
- * The @a _isr_cookie must contain the processor status returned by
- * _CPU_ISR_Disable().  The value is not modified.
- *
- * This flash code is optimal for all Nios II configurations.  The rdctl does
- * not flush the pipeline and has only a late result penalty.  The wrctl on
- * the other hand leads to a pipeline flush.
- */
-#define _CPU_ISR_Flash( _isr_cookie ) \
-  do { \
-    int _status = __builtin_rdctl( 0 ); \
-    __builtin_wrctl( 0, (int) _isr_cookie ); \
-    __builtin_wrctl( 0, _status ); \
-  } while ( 0 )
-
-bool _CPU_ISR_Is_enabled( uint32_t level );
-
-/**
- * @brief Sets the interrupt level for the executing thread.
- *
- * The valid values of @a new_level depend on the Nios II configuration.  A
- * value of zero represents enabled interrupts in all configurations.
- *
- * @see _CPU_ISR_Get_level()
- */
-void _CPU_ISR_Set_level( uint32_t new_level );
-
-/**
- * @brief Returns the interrupt level of the executing thread.
- *
- * @retval 0 Interrupts are enabled.
- * @retval otherwise The value depends on the Nios II configuration.  In case
- * of an internal interrupt controller (IIC) the only valid value is one which
- * indicates disabled interrupts.  In case of an external interrupt controller
- * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
- * to disable interrupts, then one is the only valid value indicating disabled
- * interrupts.  Secondly if the IL status field is used to disable interrupts,
- * then this value will be returned.  Interrupts are disabled at the maximum
- * level specified by the _Nios2_ISR_Status_bits.
- */
-uint32_t _CPU_ISR_Get_level( void );
-
-/**
- * @brief Initializes the CPU context.
- *
- * The following steps are performed:
- *  - setting a starting address
- *  - preparing the stack
- *  - preparing the stack and frame pointers
- *  - setting the proper interrupt level in the context
- *
- * @param[in] context points to the context area
- * @param[in] stack_area_begin is the low address of the allocated stack area
- * @param[in] stack_area_size is the size of the stack area in bytes
- * @param[in] new_level is the interrupt level for the task
- * @param[in] entry_point is the task's entry point
- * @param[in] is_fp is set to @c true if the task is a floating point task
- * @param[in] tls_area is the thread-local storage (TLS) area
- */
-void _CPU_Context_Initialize(
-  Context_Control *context,
-  void *stack_area_begin,
-  size_t stack_area_size,
-  uint32_t new_level,
-  void (*entry_point)( void ),
-  bool is_fp,
-  void *tls_area
-);
-
-#define _CPU_Context_Restart_self( _the_context ) \
-  _CPU_Context_restore( (_the_context) );
-
-void _CPU_Fatal_halt( uint32_t _source, uint32_t _error )
-  RTEMS_NO_RETURN;
-
-/**
- * @brief CPU initialization.
- */
-void _CPU_Initialize( void );
-
-/**
- * @brief CPU ISR install raw handler.
- */
-void _CPU_ISR_install_raw_handler(
-  uint32_t vector,
-  proc_ptr new_handler,
-  proc_ptr *old_handler
-);
-
-/**
- * @brief CPU ISR install vector.
- */
-void _CPU_ISR_install_vector(
-  uint32_t vector,
-  proc_ptr new_handler,
-  proc_ptr *old_handler
-);
-
-void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
-
-void _CPU_Context_restore(
-  Context_Control *new_context
-) RTEMS_NO_RETURN;
-
-void _CPU_Context_volatile_clobber( uintptr_t pattern );
-
-void _CPU_Context_validate( uintptr_t pattern );
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
-
-static inline uint32_t CPU_swap_u32( uint32_t value )
-{
-  uint32_t byte1, byte2, byte3, byte4, swapped;
-
-  byte4 = (value >> 24) & 0xff;
-  byte3 = (value >> 16) & 0xff;
-  byte2 = (value >> 8)  & 0xff;
-  byte1 =  value        & 0xff;
-
-  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
-
-  return swapped;
-}
-
-#define CPU_swap_u16( value ) \
-  (((value&0xff) << 8) | ((value >> 8)&0xff))
-
-typedef uint32_t CPU_Counter_ticks;
-
-CPU_Counter_ticks _CPU_Counter_read( void );
-
-static inline CPU_Counter_ticks _CPU_Counter_difference(
-  CPU_Counter_ticks second,
-  CPU_Counter_ticks first
-)
-{
-  return second - first;
-}
-
-#endif /* ASM */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
deleted file mode 100644
index 81a19c8d69..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/**
- * @file
- *
- * @brief Altera Nios II Assembly File
- *
- * Very loose template for an include file for the cpu_asm.? file
- * if it is implemented as a ".S" file (preprocessed by cpp) instead
- * of a ".s" file (preprocessed by gm4 or gasp).
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_CPU_ASM_H
-#define _RTEMS_SCORE_CPU_ASM_H
-
-/* pull in the generated offsets */
-
-/*
-#include <rtems/score/offsets.h>
-*/
-
-/*
- * Hardware General Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Floating Point Registers
- */
-
-/* put something here */
-
-/*
- * Hardware Control Registers
- */
-
-/* put something here */
-
-/*
- * Calling Convention
- */
-
-/* put something here */
-
-/*
- * Temporary registers
- */
-
-/* put something here */
-
-/*
- * Floating Point Registers - SW Conventions
- */
-
-/* put something here */
-
-/*
- * Temporary floating point registers
- */
-
-/* put something here */
-
-#endif
-
-/* end of file */
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h b/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h
deleted file mode 100644
index 598ee76b20..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/cpuatomic.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * COPYRIGHT (c) 2012-2013 Deng Hengyi.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
-#define _RTEMS_SCORE_ATOMIC_CPU_H
-
-#include <rtems/score/cpustdatomic.h>
-
-#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h b/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h
deleted file mode 100644
index 789f2badd9..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/cpuimpl.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/**
- * @file
- *
- * @brief CPU Port Implementation API
- */
-
-/*
- * Copyright (c) 2013 embedded brains GmbH
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_CPUIMPL_H
-#define _RTEMS_SCORE_CPUIMPL_H
-
-#include <rtems/score/cpu.h>
-
-#define CPU_PER_CPU_CONTROL_SIZE 0
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ASM */
-
-#endif /* _RTEMS_SCORE_CPUIMPL_H */
diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h b/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h
deleted file mode 100644
index bf2390a51f..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/nios2-count-zeros.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Author: Jeffrey O. Hill
- *
- * Copyright 2012. Los Alamos National Security, LLC.
- * This material was produced under U.S. Government contract
- * DE-AC52-06NA25396 for Los Alamos National Laboratory (LANL),
- * which is operated by Los Alamos National Security, LLC for
- * the U.S. Department of Energy. The U.S. Government has rights
- * to use, reproduce, and distribute this software.  NEITHER THE
- * GOVERNMENT NOR LOS ALAMOS NATIONAL SECURITY, LLC MAKES ANY
- * WARRANTY, EXPRESS OR IMPLIED, OR ASSUMES ANY LIABILITY FOR
- * THE USE OF THIS SOFTWARE.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _NIOS2_COUNT_ZEROS_H
-#define _NIOS2_COUNT_ZEROS_H
-
-#include <stdint.h>
-
-#include <rtems/score/bitfield.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/*
- * This implementation is currently much more efficient than
- * the GCC provided __builtin_clz
- */
-static inline unsigned _Nios2_Count_leading_zeros( uint32_t p )
-{
-  unsigned bitIdx;
-
-  if ( p <= 0xffffu ) {
-    if ( p < 0x100u ) {
-      bitIdx = _Bitfield_Leading_zeros[ p ] + 24u;
-    } else {
-      bitIdx = _Bitfield_Leading_zeros[ p >> 8u ] + 16u;
-    }
-  } else {
-    p >>= 16u;
-
-    if ( p < 0x100u ) {
-      bitIdx = _Bitfield_Leading_zeros[ p ] + 8u;
-    } else {
-      bitIdx = _Bitfield_Leading_zeros[ p >> 8u ];
-    }
-  }
-
-  return bitIdx;
-}
-
-/*
- * This implementation is currently much more efficient than
- * the GCC provided __builtin_ctz
- */
-static inline unsigned _Nios2_Count_trailing_zeros( uint32_t p )
-{
-  return 31u - _Nios2_Count_leading_zeros( p & ( -p ) );
-}
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* _NIOS2_COUNT_ZEROS_H */
diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h b/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
deleted file mode 100644
index d5eb4b3597..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/**
- * @file
- *
- * @brief NIOS II Utility
- */
-/*
- * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_NIOS2_UTILITY_H
-#define _RTEMS_SCORE_NIOS2_UTILITY_H
-
-#define NIOS2_CTLREG_INDEX_STATUS 0
-#define NIOS2_CTLREG_INDEX_ESTATUS 1
-#define NIOS2_CTLREG_INDEX_BSTATUS 2
-#define NIOS2_CTLREG_INDEX_IENABLE 3
-#define NIOS2_CTLREG_INDEX_IPENDING 4
-#define NIOS2_CTLREG_INDEX_CPUID 5
-#define NIOS2_CTLREG_INDEX_EXCEPTION 7
-#define NIOS2_CTLREG_INDEX_PTEADDR 8
-#define NIOS2_CTLREG_INDEX_TLBACC 9
-#define NIOS2_CTLREG_INDEX_TLBMISC 10
-#define NIOS2_CTLREG_INDEX_BADADDR 12
-#define NIOS2_CTLREG_INDEX_CONFIG 13
-#define NIOS2_CTLREG_INDEX_MPUBASE 14
-#define NIOS2_CTLREG_INDEX_MPUACC 15
-
-#define NIOS2_CONTEXT_OFFSET_R16 0
-#define NIOS2_CONTEXT_OFFSET_R17 4
-#define NIOS2_CONTEXT_OFFSET_R18 8
-#define NIOS2_CONTEXT_OFFSET_R19 12
-#define NIOS2_CONTEXT_OFFSET_R20 16
-#define NIOS2_CONTEXT_OFFSET_R21 20
-#define NIOS2_CONTEXT_OFFSET_R22 24
-#define NIOS2_CONTEXT_OFFSET_R23 28
-#define NIOS2_CONTEXT_OFFSET_FP 32
-#define NIOS2_CONTEXT_OFFSET_STATUS 36
-#define NIOS2_CONTEXT_OFFSET_SP 40
-#define NIOS2_CONTEXT_OFFSET_RA 44
-#define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48
-#define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52
-#define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56
-
-#define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe
-#define NIOS2_ISR_STATUS_BITS_IIC 0x00000000
-
-#define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f
-#define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0
-
-#define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff
-#define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000
-
-#define NIOS2_STATUS_RSIE (1 << 23)
-#define NIOS2_STATUS_NMI (1 << 22)
-#define NIOS2_STATUS_PRS_OFFSET 16
-#define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET)
-#define NIOS2_STATUS_CRS_OFFSET 10
-#define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET)
-#define NIOS2_STATUS_IL_OFFSET 4
-#define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET)
-#define NIOS2_STATUS_IH (1 << 3)
-#define NIOS2_STATUS_EH (1 << 2)
-#define NIOS2_STATUS_U (1 << 1)
-#define NIOS2_STATUS_PIE (1 << 0)
-
-#define NIOS2_EXCEPTION_CAUSE_OFFSET 2
-#define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET)
-
-#define NIOS2_PTEADDR_PTBASE_OFFSET 22
-#define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET)
-#define NIOS2_PTEADDR_VPN_OFFSET 2
-#define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET)
-
-#define NIOS2_TLBACC_IG_OFFSET 25
-#define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET)
-#define NIOS2_TLBACC_C (1 << 24)
-#define NIOS2_TLBACC_R (1 << 23)
-#define NIOS2_TLBACC_W (1 << 22)
-#define NIOS2_TLBACC_X (1 << 21)
-#define NIOS2_TLBACC_G (1 << 20)
-#define NIOS2_TLBACC_PFN_OFFSET 2
-#define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET)
-
-#define NIOS2_TLBMISC_WAY_OFFSET 20
-#define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET)
-#define NIOS2_TLBMISC_RD (1 << 19)
-#define NIOS2_TLBMISC_WE (1 << 18)
-#define NIOS2_TLBMISC_PID_OFFSET 5
-#define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET)
-#define NIOS2_TLBMISC_DBL (1 << 3)
-#define NIOS2_TLBMISC_BAD (1 << 2)
-#define NIOS2_TLBMISC_PERM (1 << 1)
-#define NIOS2_TLBMISC_D (1 << 0)
-
-#define NIOS2_CONFIG_ANI (1 << 1)
-#define NIOS2_CONFIG_PE (1 << 0)
-
-#define NIOS2_MPUBASE_BASE_OFFSET 6
-#define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET)
-#define NIOS2_MPUBASE_INDEX_OFFSET 1
-
-/* Avoid redefines with Altera HAL */
-#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e)
-
-#define NIOS2_MPUBASE_D (1 << 0)
-
-#define NIOS2_MPUACC_MASK_OFFSET 6
-
-/* Avoid redefines with Altera HAL */
-#define NIOS2_MPUACC_MASK_MASK (0x7fffffc0)
-
-#define NIOS2_MPUACC_LIMIT_OFFSET 6
-
-/* Avoid redefines with Altera HAL */
-#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0)
-
-#define NIOS2_MPUACC_C (1 << 5)
-#define NIOS2_MPUACC_PERM_OFFSET 2
-
-/* Avoid redefines with Altera HAL */
-#define NIOS2_MPUACC_PERM_MASK (0x0000001c)
-
-#define NIOS2_MPUACC_RD (1 << 1)
-#define NIOS2_MPUACC_WR (1 << 0)
-
-#ifndef ASM
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- * @brief Nios II specific thread dispatch disabled indicator.
- *
- * This global variable is used by the interrupt dispatch support for the
- * external interrupt controller (EIC) with shadow registers.  This makes it
- * possible to do the thread dispatch after an interrupt without disabled
- * interrupts and thus probably reduce the maximum interrupt latency.  Its
- * purpose is to prevent unbounded stack usage of the interrupted thread.
- */
-extern uint32_t _Nios2_Thread_dispatch_disabled;
-
-/**
- * @brief This global symbol specifies the status register mask used to disable
- * interrupts.
- *
- * The board support package must provide a global symbol with this name to
- * specify the status register mask used in _CPU_ISR_Disable().
- */
-extern char _Nios2_ISR_Status_mask [];
-
-/**
- * @brief This symbol specifies the status register bits used to disable
- * interrupts.
- *
- * The board support package must provide a global symbol with this name to
- * specify the status register bits used in _CPU_ISR_Disable().
- */
-extern char _Nios2_ISR_Status_bits [];
-
-static inline void _Nios2_Flush_pipeline( void )
-{
-  __asm__ volatile ("flushp");
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_status( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS );
-}
-
-static inline void _Nios2_Set_ctlreg_status( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_estatus( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS );
-}
-
-static inline void _Nios2_Set_ctlreg_estatus( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_bstatus( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS );
-}
-
-static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_ienable( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE );
-}
-
-static inline void _Nios2_Set_ctlreg_ienable( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_ipending( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_cpuid( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_exception( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR );
-}
-
-static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC );
-}
-
-static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC );
-}
-
-static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_badaddr( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_config( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG );
-}
-
-static inline void _Nios2_Set_ctlreg_config( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_mpubase( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE );
-}
-
-static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value );
-}
-
-static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void )
-{
-  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC );
-}
-
-static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value )
-{
-  __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value );
-}
-
-static inline uint32_t _Nios2_ISR_Get_status_mask( void )
-{
-  return (uint32_t) &_Nios2_ISR_Status_mask [0];
-}
-
-static inline uint32_t _Nios2_ISR_Get_status_bits( void )
-{
-  return (uint32_t) &_Nios2_ISR_Status_bits [0];
-}
-
-static inline bool _Nios2_Has_internal_interrupt_controller( void )
-{
-  return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC;
-}
-
-uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
-
-typedef struct {
-  int data_address_width;
-  int instruction_address_width;
-  int data_region_size_log2;
-  int instruction_region_size_log2;
-  int data_region_count;
-  int instruction_region_count;
-  int data_index_for_stack_protection;
-  bool region_uses_limit;
-  bool enable_data_cache_for_stack;
-} Nios2_MPU_Configuration;
-
-void _Nios2_MPU_Set_configuration( const Nios2_MPU_Configuration *config );
-
-const Nios2_MPU_Configuration *_Nios2_MPU_Get_configuration( void );
-
-typedef enum {
-  NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0,
-  NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE,
-  NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE,
-  NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0,
-  NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE,
-  NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY,
-  NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4,
-  NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY,
-  NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE
-} Nios2_MPU_Region_permissions;
-
-typedef struct {
-  int index;
-  const void *base;
-  const void *end;
-  Nios2_MPU_Region_permissions perm;
-  bool data;
-  bool cacheable;
-  bool read;
-  bool write;
-} Nios2_MPU_Region_descriptor;
-
-#define NIOS2_MPU_REGION_DESC_INST( index, base, end ) \
-  { \
-    (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \
-    false, false, false, true \
-  }
-
-#define NIOS2_MPU_REGION_DESC_DATA_RO( index, base, end ) \
-  { \
-    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \
-    true, true, false, true \
-  }
-
-#define NIOS2_MPU_REGION_DESC_DATA_RW( index, base, end ) \
-  { \
-    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \
-    true, true, false, true \
-  }
-
-#define NIOS2_MPU_REGION_DESC_DATA_IO( index, base, end ) \
-  { \
-    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \
-    true, false, false, true \
-  }
-
-static inline int _Nios2_MPU_Get_region_count(
-  const Nios2_MPU_Configuration *config,
-  bool data
-)
-{
-  return data ?
-    config->data_region_count
-      : config->instruction_region_count;
-}
-
-static inline bool _Nios2_MPU_Is_valid_index(
-  const Nios2_MPU_Configuration *config,
-  int index,
-  bool data
-)
-{
-  return 0 <= index
-    && index < _Nios2_MPU_Get_region_count( config, data );
-}
-
-bool _Nios2_MPU_Setup_region_registers(
-  const Nios2_MPU_Configuration *config,
-  const Nios2_MPU_Region_descriptor *desc,
-  uint32_t *mpubase,
-  uint32_t *mpuacc
-);
-
-bool _Nios2_MPU_Get_region_descriptor(
-  const Nios2_MPU_Configuration *config,
-  int index,
-  bool data,
-  Nios2_MPU_Region_descriptor *desc
-);
-
-/**
- * @brief Searches the region table part for a disabled region.
- *
- * The table will be searched between indices @a begin and @a end.  The @a end
- * index is not part of the search range.  If @a end is negative, then the
- * region count will be used.  Thus a @a begin of 0 and a @a end of -1 will
- * specify the complete table.
- *
- * @retval -1 No disabled region is available.
- * @retval other Index of disabled region.
- */
-int _Nios2_MPU_Get_disabled_region_index(
-  const Nios2_MPU_Configuration *config,
-  bool data,
-  int begin,
-  int end
-);
-
-/**
- * @brief Adds a region according to region descriptor @a desc.
- *
- * If @a force is true, then an enabled region will be overwritten.
- *
- * @retval true Successful operation.
- * @retval false Invalid region descriptor or region already in use.
- */
-bool _Nios2_MPU_Add_region(
-  const Nios2_MPU_Configuration *config,
-  const Nios2_MPU_Region_descriptor *desc,
-  bool force
-);
-
-static inline void _Nios2_MPU_Get_region_registers(
-  int index,
-  bool data,
-  uint32_t *mpubase,
-  uint32_t *mpuacc
-)
-{
-  uint32_t base = (uint32_t)
-    (((index << NIOS2_MPUBASE_INDEX_OFFSET) & NIOS2_MPUBASE_INDEX_MASK)
-      | (data ? NIOS2_MPUBASE_D : 0));
-
-  _Nios2_Set_ctlreg_mpubase( base );
-  _Nios2_Set_ctlreg_mpuacc( NIOS2_MPUACC_RD );
-  _Nios2_Flush_pipeline();
-  *mpubase = _Nios2_Get_ctlreg_mpubase() | base;
-  *mpuacc = _Nios2_Get_ctlreg_mpuacc();
-}
-
-static inline void _Nios2_MPU_Set_region_registers(
-  uint32_t mpubase,
-  uint32_t mpuacc
-)
-{
-  _Nios2_Set_ctlreg_mpubase( mpubase );
-  _Nios2_Set_ctlreg_mpuacc( mpuacc );
-  _Nios2_Flush_pipeline();
-}
-
-static inline void _Nios2_MPU_Enable( void )
-{
-  uint32_t config = _Nios2_Get_ctlreg_config();
-
-  _Nios2_Set_ctlreg_config( config | NIOS2_CONFIG_PE );
-}
-
-static inline uint32_t _Nios2_MPU_Disable( void )
-{
-  uint32_t config = _Nios2_Get_ctlreg_config();
-  uint32_t config_pe = NIOS2_CONFIG_PE;
-
-  _Nios2_Set_ctlreg_config( config & ~config_pe );
-
-  return config;
-}
-
-static inline void _Nios2_MPU_Restore( uint32_t config )
-{
-  _Nios2_Set_ctlreg_config( config );
-}
-
-uint32_t _Nios2_MPU_Disable_protected( void );
-
-void _Nios2_MPU_Reset( const Nios2_MPU_Configuration *config );
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#else /* ASM */
-
-	.macro	NIOS2_ASM_DISABLE_INTERRUPTS new_status, current_status
-	movhi	\new_status, %hiadj(_Nios2_ISR_Status_mask)
-	addi	\new_status, \new_status, %lo(_Nios2_ISR_Status_mask)
-	and	\new_status, \current_status, \new_status
-	ori	\new_status, \new_status, %lo(_Nios2_ISR_Status_bits)
-	wrctl	status, \new_status
-	.endm
-
-#endif /* ASM */
-
-#endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */
diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2.h b/cpukit/score/cpu/nios2/rtems/score/nios2.h
deleted file mode 100644
index 26d76bcbfa..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/nios2.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- * @file
- *
- * @brief NIOS II Set up Basic CPU Dependency Settings Based on
- * Compiler Settings
- *
- * This file sets up basic CPU dependency settings based on
- * compiler settings.  For example, it can determine if
- * floating point is available.  This particular implementation
- * is specific to the NIOS2 port.
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef _RTEMS_SCORE_NIOS2_H
-#define _RTEMS_SCORE_NIOS2_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This file contains the information required to build
- *  RTEMS for a particular member of the NIOS2 family.
- *  It does this by setting variables to indicate which
- *  implementation dependent features are present in a particular
- *  member of the family.
- *
- *  This is a good place to list all the known CPU models
- *  that this port supports and which RTEMS CPU model they correspond
- *  to.
- */
-
-/*
- *  Define the name of the CPU family and specific model.
- */
-
-#define CPU_NAME "NIOS2"
-#define CPU_MODEL_NAME "nios2"
-
-/*
- *  See also nios2-rtems-gcc -print-multi-lib for all valid combinations of
- *
- *    -mno-hw-mul
- *    -mhw-mulx
- *    -mstack-check
- *    -pg
- *    -EB
- *    -mcustom-fpu-cfg=60-1
- *    -mcustom-fpu-cfg=60-2
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _RTEMS_SCORE_NIOS2_H */
diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h
deleted file mode 100644
index 23cf39419b..0000000000
--- a/cpukit/score/cpu/nios2/rtems/score/types.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
- * @file
- *
- * @brief Altera Nios II CPU Type Definitions
- *
- * This include file contains type definitions pertaining to the
- * Altera Nios II processor family.
- */
-
-/*
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef _RTEMS_SCORE_TYPES_H
-#define _RTEMS_SCORE_TYPES_H
-
-#include <rtems/score/basedefs.h>
-
-#ifndef ASM
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- *  This section defines the basic types for this processor.
- */
-
-/** Type that can store a 32-bit integer or a pointer. */
-typedef uintptr_t CPU_Uint32ptr;
-
-typedef void nios2_isr;
-typedef void ( *nios2_isr_entry )( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* !ASM */
-
-#endif