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| author | Chris Johns <chrisj@rtems.org> | 2011-08-18 09:00:14 +0000 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2011-08-18 09:00:14 +0000 |
| commit | a3854892811dbf4e8d36fb6666c19e472d10d787 (patch) | |
| tree | 8e135e5a7c0329b79a6865a956f893449c7926e2 /cpukit/score/cpu/nios2/nios2-iic-low-level.S | |
| parent | 2011-08-18 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff) | |
| download | rtems-a3854892811dbf4e8d36fb6666c19e472d10d787.tar.bz2 | |
2011-08-18 Chris Johns <chrisj@rtems.org>
* cpu.c: Fix the ISR get level for the IIC. Make
_CPU_Context_Initialize a function rather than inlined.
* cpu_asm.S: Do not enable interrupt on return, rather resume the
state on entry to the ISR.
* irq.c, nios2/nios2-iic-low-level.S: Change the ISR handler so
the ipending decoding is in C and within the interrupt
context. This is usable with the Altera HAL directly.
* rtems/score/cpu.h: Add ienable and ipending interfaces. Add some
comments. Remove _CPU_Context_Initialize.
Diffstat (limited to 'cpukit/score/cpu/nios2/nios2-iic-low-level.S')
| -rw-r--r-- | cpukit/score/cpu/nios2/nios2-iic-low-level.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/cpukit/score/cpu/nios2/nios2-iic-low-level.S b/cpukit/score/cpu/nios2/nios2-iic-low-level.S index 7a5d24ca59..0196cf98e3 100644 --- a/cpukit/score/cpu/nios2/nios2-iic-low-level.S +++ b/cpukit/score/cpu/nios2/nios2-iic-low-level.S @@ -231,6 +231,7 @@ _ISR_Handler: stw et, 68(sp) stw ea, 72(sp) +#if REMOVED_BY_CCJ /* * Obtain a bitlist of the pending interrupts. */ @@ -266,7 +267,8 @@ _ISR_Handler: */ mov r5, sp - +#endif + .extern __ISR_Handler call __ISR_Handler |