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authorJoel Sherrill <joel.sherrill@OARcorp.com>2001-05-22 22:59:42 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2001-05-22 22:59:42 +0000
commite2040badd22f8ad392976d324d1a8daa953e926f (patch)
tree6d3d5c198e6e89bc781c21f41a6083d7926d5e48 /cpukit/score/cpu/mips/rtems/score/mips.h
parentbaf22b93bd1e5796e7140f8ca6311bc4422af335 (diff)
downloadrtems-e2040badd22f8ad392976d324d1a8daa953e926f.tar.bz2
2001-05-22 Greg Menke <gregory.menke@gsfc.nasa.gov>
* rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks. * rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31(). * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
Diffstat (limited to '')
-rw-r--r--cpukit/score/cpu/mips/rtems/score/mips.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h
index 0527721b8c..ce772adac6 100644
--- a/cpukit/score/cpu/mips/rtems/score/mips.h
+++ b/cpukit/score/cpu/mips/rtems/score/mips.h
@@ -90,6 +90,42 @@ extern "C" {
asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
} while (0)
+
+
+
+
+#define mips_get_cause( _x ) \
+ do { \
+ asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
+ } while (0)
+
+
+#define mips_set_cause( _x ) \
+ do { \
+ register unsigned int __x = (_x); \
+ asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
+ } while (0)
+
+
+
+
+
+#define mips_get_fcr31( _x ) \
+ do { \
+ asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
+ } while(0)
+
+
+#define mips_set_fcr31( _x ) \
+ do { \
+ register unsigned int __x = (_x); \
+ asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
+ } while(0)
+
+
+
+
+
/*
* Manipulate interrupt mask
*