From e2040badd22f8ad392976d324d1a8daa953e926f Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 22 May 2001 22:59:42 +0000 Subject: 2001-05-22 Greg Menke * rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks. * rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31(). * Assisted in design and debug by Joel Sherrill . --- cpukit/score/cpu/mips/rtems/score/mips.h | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'cpukit/score/cpu/mips/rtems/score/mips.h') diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 0527721b8c..ce772adac6 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -90,6 +90,42 @@ extern "C" { asm volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \ } while (0) + + + + +#define mips_get_cause( _x ) \ + do { \ + asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_cause( _x ) \ + do { \ + register unsigned int __x = (_x); \ + asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \ + } while (0) + + + + + +#define mips_get_fcr31( _x ) \ + do { \ + asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \ + } while(0) + + +#define mips_set_fcr31( _x ) \ + do { \ + register unsigned int __x = (_x); \ + asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \ + } while(0) + + + + + /* * Manipulate interrupt mask * -- cgit v1.2.3