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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-03-14 00:14:18 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2001-03-14 00:14:18 +0000 |
| commit | 2e549dad4b695ddf4de9ea4a2e68130a142bc67a (patch) | |
| tree | eff6a91bab8b8354628829f9d0977b8e0704ae51 /cpukit/score/cpu/mips/rtems/score/mips.h | |
| parent | 2001-01-31 Sergei Organov <osv@javad.ru> (diff) | |
| download | rtems-2e549dad4b695ddf4de9ea4a2e68130a142bc67a.tar.bz2 | |
2001-03-13 Joel Sherrill <joel@OARcorp.com>
* cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
Also reimplemented some assembly routines in C further reducing
the amount of assembly and increasing maintainability.
Diffstat (limited to 'cpukit/score/cpu/mips/rtems/score/mips.h')
| -rw-r--r-- | cpukit/score/cpu/mips/rtems/score/mips.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 4ef807971d..042ed16a88 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -30,12 +30,16 @@ extern "C" { #if __mips == 3 #ifdef ASM -#define SR_INTERRUPT_ENABLE_BITS 0x03 +#define SR_INTERRUPT_ENABLE_BITS 0x01 #else -#define SR_INTERRUPT_ENABLE_BITS SR_IE|SR_EXL +#define SR_INTERRUPT_ENABLE_BITS SR_IE #endif -#else + +#elif __mips == 1 #define SR_INTERRUPT_ENABLE_BITS SR_IEC + +#else +#error "mips interrupt enable bits: unknown architecture level!" #endif /* |