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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-03-01 16:21:12 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-03-01 16:21:12 +0000
commitbd1ecb00d955204b7c01daffe7e6e7cb8c8a765a (patch)
tree0a3497019e1d4840c978d664a05107d00ddc69b5 /cpukit/score/cpu/mips/rtems/mips/idtcpu.h
parent2001-03-01 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-bd1ecb00d955204b7c01daffe7e6e7cb8c8a765a.tar.bz2
2002-02-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
* cpu_asm.S: Fixed exception return address, modified FP context switch so FPU is properly enabled and also doesn't screw up the exception FP handling. * idtcpu.h: Added C0_TAR, the MIPS target address register used for returning from exceptions. * iregdef.h: Added R_TAR to the stack frame so the target address can be saved on a per-exception basis. The new entry is past the end of the frame gdb cares about, so doesn't affect gdb or cpu.h stuff. * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it to obtain FPU defines without systax errors generated by the C defintions. * cpu.c: Improved interrupt level saves & restores.
Diffstat (limited to 'cpukit/score/cpu/mips/rtems/mips/idtcpu.h')
-rw-r--r--cpukit/score/cpu/mips/rtems/mips/idtcpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
index 90d09a104d..2f450b21b1 100644
--- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
@@ -362,6 +362,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
* Cause Register
*/
#define CAUSE_BD 0x80000000 /* Branch delay slot */
+#define CAUSE_BT 0x40000000 /* Branch Taken */
#define CAUSE_CEMASK 0x30000000 /* coprocessor error */
#define CAUSE_CESHIFT 28
@@ -393,6 +394,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define C0_WIRED $6 /* number of wired tlb entries */
#endif
+#if __mips == 1
+#define C0_TAR $6
+#endif
+
#define C0_BADVADDR $8 /* bad virtual address */
#if __mips == 3