Replace M68K_COLDFIRE_ARCH with __mcoldfire__.

3 files changed, 19 insertions, 20 deletions

diff --git a/cpukit/score/cpu/m68k/cpu_asm.S b/cpukit/score/cpu/m68k/cpu_asm.S
index e53816dde3..772845f594 100644
--- a/cpukit/score/cpu/m68k/cpu_asm.S
+++ b/cpukit/score/cpu/m68k/cpu_asm.S
@@ -107,7 +107,7 @@ norst:  frestore a0@+                     | restore the fp state frame
  *    transfer control to the interrupt dispatcher.
  */
 
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 .set SR_OFFSET,    2                     | Status register offset
 .set PC_OFFSET,    4                     | Program Counter offset
 .set FVO_OFFSET,   0                     | Format/vector offset
@@ -128,7 +128,7 @@ norst:  frestore a0@+                     | restore the fp state frame
 
 SYM (_ISR_Handler):
         addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
-#if ( M68K_COLDFIRE_ARCH == 0 )
+#if ( !defined(__mcoldfire__) )
         moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
 #else
 	lea	a7@(-SAVED),a7
@@ -192,7 +192,7 @@ SYM (_ISR_Handler):
  * see if it is _ISR_Handler.  If it is we have the case of nesting interrupts
  * without the dispatch level being incremented.
  */
-  #if ( M68K_COLDFIRE_ARCH == 0 && M68K_MC68060_ARCH == 0 )
+  #if ( !defined(__mcoldfire__) && M68K_MC68060_ARCH == 0 )
         cmpl    #_ISR_Handler,a7@(SAVED+PC_OFFSET)
         beq.b   exit        
   #endif
@@ -218,7 +218,7 @@ bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
         jsr SYM (_Thread_Dispatch)       | Perform context switch
 #endif
 
-#if ( M68K_COLDFIRE_ARCH == 0 )
+#if ( !defined(__mcoldfire__) )
 exit:   moveml  a7@+,d0-d1/a0-a1	 | restore d0-d1,a0-a1
 #else
 exit:	moveml	a7@,d0-d1/a0-a1		 | restore d0-d1,a0-a1
@@ -247,7 +247,7 @@ exit:	moveml	a7@,d0-d1/a0-a1		 | restore d0-d1,a0-a1
 
         .global SYM (_ISR_Dispatch)
 SYM (_ISR_Dispatch):
-#if ( M68K_COLDFIRE_ARCH == 0 )
+#if ( !defined(__mcoldfire__) )
         movml   d0-d1/a0-a1,a7@-
         jsr     SYM (_Thread_Dispatch)
         movml   a7@+,d0-d1/a0-a1
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index 7f682f9fa6..a973e406ab 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -436,7 +436,7 @@ void _CPU_Thread_Idle_body( void );
  *    + disable interrupts and halt the CPU
  */
 
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 #define _CPU_Fatal_halt( _error ) \
   { asm volatile( "move.w %%sr,%%d0\n\t" \
 		  "or.l %2,%%d0\n\t" \
@@ -494,7 +494,7 @@ void _CPU_Thread_Idle_body( void );
 /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
    _CPU_Priority_bits_index is not needed), handles the 0 case, and
    does not molest _value -- jsg */
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
   { \
     extern const unsigned char __BFFFOtable[256]; \
diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h
index 54f566df42..f12322f1e4 100644
--- a/cpukit/score/cpu/m68k/rtems/score/m68k.h
+++ b/cpukit/score/cpu/m68k/rtems/score/m68k.h
@@ -208,7 +208,6 @@ extern "C" {
 #define M68K_HAS_MISALIGNED      1
 #define M68K_HAS_FPU             0
 #define M68K_HAS_FPSP_PACKAGE    0
-#define M68K_COLDFIRE_ARCH       1
 #define M68K_HAS_ISA_APLUS       1
 
 #elif defined(__mcf5200__)
@@ -222,7 +221,6 @@ extern "C" {
 #define M68K_HAS_MISALIGNED      1
 #define M68K_HAS_FPU             0
 #define M68K_HAS_FPSP_PACKAGE    0
-#define M68K_COLDFIRE_ARCH       1
 #define M68K_HAS_ISA_APLUS       0
 
 #elif defined(__mc68000__)
@@ -254,19 +252,20 @@ extern "C" {
 #endif
 
 /*
- *  If the above did not specify a ColdFire architecture, then set
- *  this flag to indicate that it is not a ColdFire CPU.
+ * OBSOLETE: Backward compatibility only - Don't use.
+ * Use __mcoldfire__ instead.
  */
-
-#if !defined(M68K_COLDFIRE_ARCH)
-#define M68K_COLDFIRE_ARCH       0
+#if defined(__mcoldfire__)
+#define M68K_COLDFIRE_ARCH      1
+#else
+#define M68K_COLDFIRE_ARCH	0
 #endif
 
 /*
  *  Define the name of the CPU family.
  */
 
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
   #define CPU_NAME "Motorola ColdFire"
 #else
   #define CPU_NAME "Motorola MC68xxx"
@@ -274,7 +273,7 @@ extern "C" {
 
 #ifndef ASM
 
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 #define m68k_disable_interrupts( _level ) \
    do { register uint32_t   _tmpsr = 0x0700; \
         asm volatile ( "move.w %%sr,%0\n\t" \
@@ -294,7 +293,7 @@ extern "C" {
 #define m68k_enable_interrupts( _level ) \
   asm volatile ( "move.w  %0,%%sr " : : "d" (_level) : "cc");
 
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 #define m68k_flash_interrupts( _level ) \
    do { register uint32_t   _tmpsr = 0x0700; \
 	asm volatile ( "move.w %2,%%sr\n\t" \
@@ -328,14 +327,14 @@ extern "C" {
     asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
   } while (0)
 
-#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
+#if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) )
 #define m68k_get_vbr( vbr ) \
   asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
 
 #define m68k_set_vbr( vbr ) \
   asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
 
-#elif ( M68K_COLDFIRE_ARCH == 1 )
+#elif ( defined(__mcoldfire__) )
 extern void*                     _VBR; 
 #define m68k_get_vbr( _vbr ) _vbr = &_VBR
 
@@ -354,7 +353,7 @@ extern void*                     _VBR;
  *  The following routine swaps the endian format of an unsigned int.
  *  It must be static because it is referenced indirectly.
  */
-#if ( M68K_COLDFIRE_ARCH == 1 )
+#if ( defined(__mcoldfire__) )
 
 /* There are no rotate commands in Coldfire architecture. We will use
  * generic implementation of endian swapping for Coldfire.