diff options
author | cvs2git <rtems-devel@rtems.org> | 1996-01-24 20:38:48 +0000 |
---|---|---|
committer | cvs2git <rtems-devel@rtems.org> | 1996-01-24 20:38:48 +0000 |
commit | c5cea43cde3772505263e312ae97c5858d918d8f (patch) | |
tree | 4e594f67b38fc8cc2d200fc0c61d65a0a591ea52 /cpukit/score/cpu/m68k | |
parent | M==military changed to M=multiprocessor (diff) | |
download | rtems-3.5.1.tar.bz2 |
This commit was manufactured by cvs2svn to create tag 'rtems-3-5-1'.3.5.1
Sprout from master 1996-01-24 20:38:47 UTC Joel Sherrill <joel.sherrill@OARcorp.com> 'M==military changed to M=multiprocessor'
Delete:
c/build-tools/README
c/build-tools/cklength.c
c/build-tools/eolstrip.c
c/build-tools/packhex.c
c/build-tools/unhex.c
c/src/exec/libcsupport/include/clockdrv.h
c/src/exec/libcsupport/include/console.h
c/src/exec/libcsupport/include/iosupp.h
c/src/exec/libcsupport/include/ringbuf.h
c/src/exec/libcsupport/include/rtems/assoc.h
c/src/exec/libcsupport/include/rtems/error.h
c/src/exec/libcsupport/include/rtems/libcsupport.h
c/src/exec/libcsupport/include/rtems/libio.h
c/src/exec/libcsupport/include/spurious.h
c/src/exec/libcsupport/include/sys/utsname.h
c/src/exec/libcsupport/include/timerdrv.h
c/src/exec/libcsupport/include/vmeintr.h
c/src/exec/libcsupport/src/README
c/src/exec/libcsupport/src/__brk.c
c/src/exec/libcsupport/src/__gettod.c
c/src/exec/libcsupport/src/__times.c
c/src/exec/libcsupport/src/assoc.c
c/src/exec/libcsupport/src/error.c
c/src/exec/libcsupport/src/hosterr.c
c/src/exec/libcsupport/src/libio.c
c/src/exec/libcsupport/src/malloc.c
c/src/exec/libcsupport/src/newlibc.c
c/src/exec/libcsupport/src/no_libc.c
c/src/exec/libcsupport/src/unixlibc.c
c/src/exec/libcsupport/src/utsname.c
c/src/exec/posix/base/aio.h
c/src/exec/posix/base/devctl.h
c/src/exec/posix/base/intr.h
c/src/exec/posix/base/limits.h
c/src/exec/posix/base/mqueue.h
c/src/exec/posix/base/pthread.h
c/src/exec/posix/base/sched.h
c/src/exec/posix/base/semaphore.h
c/src/exec/posix/base/unistd.h
c/src/exec/posix/headers/cancel.h
c/src/exec/posix/headers/cond.h
c/src/exec/posix/headers/condmp.h
c/src/exec/posix/headers/intr.h
c/src/exec/posix/headers/key.h
c/src/exec/posix/headers/mqueue.h
c/src/exec/posix/headers/mqueuemp.h
c/src/exec/posix/headers/mutex.h
c/src/exec/posix/headers/mutexmp.h
c/src/exec/posix/headers/priority.h
c/src/exec/posix/headers/pthread.h
c/src/exec/posix/headers/pthreadmp.h
c/src/exec/posix/headers/semaphore.h
c/src/exec/posix/headers/semaphoremp.h
c/src/exec/posix/headers/threadsup.h
c/src/exec/posix/headers/time.h
c/src/exec/posix/include/aio.h
c/src/exec/posix/include/devctl.h
c/src/exec/posix/include/intr.h
c/src/exec/posix/include/limits.h
c/src/exec/posix/include/mqueue.h
c/src/exec/posix/include/pthread.h
c/src/exec/posix/include/rtems/posix/cancel.h
c/src/exec/posix/include/rtems/posix/cond.h
c/src/exec/posix/include/rtems/posix/condmp.h
c/src/exec/posix/include/rtems/posix/intr.h
c/src/exec/posix/include/rtems/posix/key.h
c/src/exec/posix/include/rtems/posix/mqueue.h
c/src/exec/posix/include/rtems/posix/mqueuemp.h
c/src/exec/posix/include/rtems/posix/mutex.h
c/src/exec/posix/include/rtems/posix/mutexmp.h
c/src/exec/posix/include/rtems/posix/priority.h
c/src/exec/posix/include/rtems/posix/pthread.h
c/src/exec/posix/include/rtems/posix/pthreadmp.h
c/src/exec/posix/include/rtems/posix/semaphore.h
c/src/exec/posix/include/rtems/posix/semaphoremp.h
c/src/exec/posix/include/rtems/posix/threadsup.h
c/src/exec/posix/include/rtems/posix/time.h
c/src/exec/posix/include/sched.h
c/src/exec/posix/include/semaphore.h
c/src/exec/posix/include/sys/utsname.h
c/src/exec/posix/include/unistd.h
c/src/exec/posix/inline/cond.inl
c/src/exec/posix/inline/intr.inl
c/src/exec/posix/inline/key.inl
c/src/exec/posix/inline/mqueue.inl
c/src/exec/posix/inline/mutex.inl
c/src/exec/posix/inline/priority.inl
c/src/exec/posix/inline/pthread.inl
c/src/exec/posix/inline/rtems/posix/cond.inl
c/src/exec/posix/inline/rtems/posix/intr.inl
c/src/exec/posix/inline/rtems/posix/key.inl
c/src/exec/posix/inline/rtems/posix/mqueue.inl
c/src/exec/posix/inline/rtems/posix/mutex.inl
c/src/exec/posix/inline/rtems/posix/priority.inl
c/src/exec/posix/inline/rtems/posix/pthread.inl
c/src/exec/posix/inline/rtems/posix/semaphore.inl
c/src/exec/posix/inline/semaphore.inl
c/src/exec/posix/src/aio.c
c/src/exec/posix/src/cancel.c
c/src/exec/posix/src/cond.c
c/src/exec/posix/src/devctl.c
c/src/exec/posix/src/intr.c
c/src/exec/posix/src/key.c
c/src/exec/posix/src/mqueue.c
c/src/exec/posix/src/mutex.c
c/src/exec/posix/src/psignal.c
c/src/exec/posix/src/pthread.c
c/src/exec/posix/src/sched.c
c/src/exec/posix/src/semaphore.c
c/src/exec/posix/src/time.c
c/src/exec/posix/src/types.c
c/src/exec/posix/src/unistd.c
c/src/exec/posix/src/utsname.c
c/src/exec/posix/sys/utsname.h
c/src/exec/rtems/include/rtems.h
c/src/exec/rtems/include/rtems/rtems/asr.h
c/src/exec/rtems/include/rtems/rtems/attr.h
c/src/exec/rtems/include/rtems/rtems/clock.h
c/src/exec/rtems/include/rtems/rtems/dpmem.h
c/src/exec/rtems/include/rtems/rtems/event.h
c/src/exec/rtems/include/rtems/rtems/eventmp.h
c/src/exec/rtems/include/rtems/rtems/eventset.h
c/src/exec/rtems/include/rtems/rtems/intr.h
c/src/exec/rtems/include/rtems/rtems/message.h
c/src/exec/rtems/include/rtems/rtems/modes.h
c/src/exec/rtems/include/rtems/rtems/mp.h
c/src/exec/rtems/include/rtems/rtems/msgmp.h
c/src/exec/rtems/include/rtems/rtems/options.h
c/src/exec/rtems/include/rtems/rtems/part.h
c/src/exec/rtems/include/rtems/rtems/partmp.h
c/src/exec/rtems/include/rtems/rtems/ratemon.h
c/src/exec/rtems/include/rtems/rtems/region.h
c/src/exec/rtems/include/rtems/rtems/regionmp.h
c/src/exec/rtems/include/rtems/rtems/rtemsapi.h
c/src/exec/rtems/include/rtems/rtems/sem.h
c/src/exec/rtems/include/rtems/rtems/semmp.h
c/src/exec/rtems/include/rtems/rtems/signal.h
c/src/exec/rtems/include/rtems/rtems/signalmp.h
c/src/exec/rtems/include/rtems/rtems/status.h
c/src/exec/rtems/include/rtems/rtems/support.h
c/src/exec/rtems/include/rtems/rtems/taskmp.h
c/src/exec/rtems/include/rtems/rtems/tasks.h
c/src/exec/rtems/include/rtems/rtems/timer.h
c/src/exec/rtems/include/rtems/rtems/types.h
c/src/exec/rtems/inline/rtems/rtems/asr.inl
c/src/exec/rtems/inline/rtems/rtems/attr.inl
c/src/exec/rtems/inline/rtems/rtems/dpmem.inl
c/src/exec/rtems/inline/rtems/rtems/event.inl
c/src/exec/rtems/inline/rtems/rtems/eventset.inl
c/src/exec/rtems/inline/rtems/rtems/message.inl
c/src/exec/rtems/inline/rtems/rtems/modes.inl
c/src/exec/rtems/inline/rtems/rtems/options.inl
c/src/exec/rtems/inline/rtems/rtems/part.inl
c/src/exec/rtems/inline/rtems/rtems/ratemon.inl
c/src/exec/rtems/inline/rtems/rtems/region.inl
c/src/exec/rtems/inline/rtems/rtems/sem.inl
c/src/exec/rtems/inline/rtems/rtems/status.inl
c/src/exec/rtems/inline/rtems/rtems/support.inl
c/src/exec/rtems/inline/rtems/rtems/tasks.inl
c/src/exec/rtems/inline/rtems/rtems/timer.inl
c/src/exec/rtems/macros/rtems/rtems/asr.inl
c/src/exec/rtems/macros/rtems/rtems/attr.inl
c/src/exec/rtems/macros/rtems/rtems/dpmem.inl
c/src/exec/rtems/macros/rtems/rtems/event.inl
c/src/exec/rtems/macros/rtems/rtems/eventset.inl
c/src/exec/rtems/macros/rtems/rtems/message.inl
c/src/exec/rtems/macros/rtems/rtems/modes.inl
c/src/exec/rtems/macros/rtems/rtems/options.inl
c/src/exec/rtems/macros/rtems/rtems/part.inl
c/src/exec/rtems/macros/rtems/rtems/ratemon.inl
c/src/exec/rtems/macros/rtems/rtems/region.inl
c/src/exec/rtems/macros/rtems/rtems/sem.inl
c/src/exec/rtems/macros/rtems/rtems/status.inl
c/src/exec/rtems/macros/rtems/rtems/support.inl
c/src/exec/rtems/macros/rtems/rtems/tasks.inl
c/src/exec/rtems/macros/rtems/rtems/timer.inl
c/src/exec/rtems/src/rtclock.c
c/src/exec/rtems/src/rtemstimer.c
c/src/exec/sapi/headers/confdefs.h
c/src/exec/sapi/include/confdefs.h
c/src/exec/sapi/include/rtems/config.h
c/src/exec/sapi/include/rtems/directives.h
c/src/exec/sapi/include/rtems/extension.h
c/src/exec/sapi/include/rtems/fatal.h
c/src/exec/sapi/include/rtems/init.h
c/src/exec/sapi/include/rtems/io.h
c/src/exec/sapi/include/rtems/mptables.h
c/src/exec/sapi/include/rtems/sptables.h
c/src/exec/sapi/inline/rtems/extension.inl
c/src/exec/sapi/macros/rtems/extension.inl
c/src/exec/sapi/src/exinit.c
c/src/exec/score/cpu/hppa1.1/cpu.c
c/src/exec/score/cpu/hppa1.1/cpu.h
c/src/exec/score/cpu/hppa1.1/cpu_asm.h
c/src/exec/score/cpu/hppa1.1/cpu_asm.s
c/src/exec/score/cpu/hppa1.1/hppa.h
c/src/exec/score/cpu/hppa1.1/hppatypes.h
c/src/exec/score/cpu/hppa1.1/rtems.s
c/src/exec/score/cpu/powerpc/README
c/src/exec/score/cpu/powerpc/TODO
c/src/exec/score/cpu/powerpc/cpu.c
c/src/exec/score/cpu/powerpc/cpu.h
c/src/exec/score/cpu/powerpc/cpu_asm.s
c/src/exec/score/cpu/powerpc/irq_stub.s
c/src/exec/score/cpu/powerpc/ppc.h
c/src/exec/score/cpu/powerpc/ppctypes.h
c/src/exec/score/cpu/powerpc/rtems.s
c/src/exec/score/cpu/sparc/README
c/src/exec/score/cpu/sparc/asm.h
c/src/exec/score/cpu/sparc/cpu.c
c/src/exec/score/cpu/sparc/cpu.h
c/src/exec/score/cpu/sparc/cpu_asm.s
c/src/exec/score/cpu/sparc/erc32.h
c/src/exec/score/cpu/sparc/rtems.s
c/src/exec/score/cpu/sparc/sparc.h
c/src/exec/score/cpu/sparc/sparctypes.h
c/src/exec/score/include/rtems/debug.h
c/src/exec/score/include/rtems/score/address.h
c/src/exec/score/include/rtems/score/apiext.h
c/src/exec/score/include/rtems/score/bitfield.h
c/src/exec/score/include/rtems/score/chain.h
c/src/exec/score/include/rtems/score/context.h
c/src/exec/score/include/rtems/score/copyrt.h
c/src/exec/score/include/rtems/score/coremsg.h
c/src/exec/score/include/rtems/score/coremutex.h
c/src/exec/score/include/rtems/score/coresem.h
c/src/exec/score/include/rtems/score/heap.h
c/src/exec/score/include/rtems/score/interr.h
c/src/exec/score/include/rtems/score/isr.h
c/src/exec/score/include/rtems/score/mpci.h
c/src/exec/score/include/rtems/score/mppkt.h
c/src/exec/score/include/rtems/score/object.h
c/src/exec/score/include/rtems/score/objectmp.h
c/src/exec/score/include/rtems/score/priority.h
c/src/exec/score/include/rtems/score/stack.h
c/src/exec/score/include/rtems/score/states.h
c/src/exec/score/include/rtems/score/sysstate.h
c/src/exec/score/include/rtems/score/thread.h
c/src/exec/score/include/rtems/score/threadmp.h
c/src/exec/score/include/rtems/score/threadq.h
c/src/exec/score/include/rtems/score/tod.h
c/src/exec/score/include/rtems/score/tqdata.h
c/src/exec/score/include/rtems/score/userext.h
c/src/exec/score/include/rtems/score/watchdog.h
c/src/exec/score/include/rtems/score/wkspace.h
c/src/exec/score/include/rtems/system.h
c/src/exec/score/inline/rtems/score/address.inl
c/src/exec/score/inline/rtems/score/chain.inl
c/src/exec/score/inline/rtems/score/coremsg.inl
c/src/exec/score/inline/rtems/score/coremutex.inl
c/src/exec/score/inline/rtems/score/coresem.inl
c/src/exec/score/inline/rtems/score/heap.inl
c/src/exec/score/inline/rtems/score/isr.inl
c/src/exec/score/inline/rtems/score/mppkt.inl
c/src/exec/score/inline/rtems/score/object.inl
c/src/exec/score/inline/rtems/score/objectmp.inl
c/src/exec/score/inline/rtems/score/priority.inl
c/src/exec/score/inline/rtems/score/stack.inl
c/src/exec/score/inline/rtems/score/states.inl
c/src/exec/score/inline/rtems/score/sysstate.inl
c/src/exec/score/inline/rtems/score/thread.inl
c/src/exec/score/inline/rtems/score/threadmp.inl
c/src/exec/score/inline/rtems/score/tod.inl
c/src/exec/score/inline/rtems/score/tqdata.inl
c/src/exec/score/inline/rtems/score/userext.inl
c/src/exec/score/inline/rtems/score/watchdog.inl
c/src/exec/score/inline/rtems/score/wkspace.inl
c/src/exec/score/macros/rtems/score/README
c/src/exec/score/macros/rtems/score/address.inl
c/src/exec/score/macros/rtems/score/chain.inl
c/src/exec/score/macros/rtems/score/coremsg.inl
c/src/exec/score/macros/rtems/score/coremutex.inl
c/src/exec/score/macros/rtems/score/coresem.inl
c/src/exec/score/macros/rtems/score/heap.inl
c/src/exec/score/macros/rtems/score/isr.inl
c/src/exec/score/macros/rtems/score/mppkt.inl
c/src/exec/score/macros/rtems/score/object.inl
c/src/exec/score/macros/rtems/score/objectmp.inl
c/src/exec/score/macros/rtems/score/priority.inl
c/src/exec/score/macros/rtems/score/stack.inl
c/src/exec/score/macros/rtems/score/states.inl
c/src/exec/score/macros/rtems/score/sysstate.inl
c/src/exec/score/macros/rtems/score/thread.inl
c/src/exec/score/macros/rtems/score/threadmp.inl
c/src/exec/score/macros/rtems/score/tod.inl
c/src/exec/score/macros/rtems/score/tqdata.inl
c/src/exec/score/macros/rtems/score/userext.inl
c/src/exec/score/macros/rtems/score/watchdog.inl
c/src/exec/score/macros/rtems/score/wkspace.inl
c/src/exec/score/src/coretod.c
c/src/exec/score/tools/hppa1.1/genoffsets.c
c/src/lib/include/rtems/assoc.h
c/src/lib/include/rtems/error.h
c/src/lib/include/rtems/libcsupport.h
c/src/lib/include/rtems/libio.h
c/src/lib/include/sys/utsname.h
c/src/lib/libbsp/hppa1.1/simhppa/include/bsp.h
c/src/lib/libbsp/hppa1.1/simhppa/include/coverhd.h
c/src/lib/libbsp/hppa1.1/simhppa/include/ttydrv.h
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/README
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/addrconv.c
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/getcfg.c
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/intr.c
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/lock.c
c/src/lib/libbsp/hppa1.1/simhppa/shmsupp/mpisr.c
c/src/lib/libbsp/hppa1.1/simhppa/startup/bspclean.c
c/src/lib/libbsp/hppa1.1/simhppa/startup/bspstart.c
c/src/lib/libbsp/hppa1.1/simhppa/startup/setvec.c
c/src/lib/libbsp/hppa1.1/simhppa/times
c/src/lib/libbsp/hppa1.1/simhppa/tools/print_dump.c
c/src/lib/libbsp/hppa1.1/simhppa/tty/tty.c
c/src/lib/libbsp/powerpc/papyrus/README
c/src/lib/libbsp/powerpc/papyrus/dlentry/dlentry.s
c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s
c/src/lib/libbsp/powerpc/papyrus/include/bsp.h
c/src/lib/libbsp/powerpc/papyrus/include/coverhd.h
c/src/lib/libbsp/powerpc/papyrus/startup/bspclean.c
c/src/lib/libbsp/powerpc/papyrus/startup/bspstart.c
c/src/lib/libbsp/powerpc/papyrus/startup/linkcmds
c/src/lib/libbsp/powerpc/papyrus/startup/setvec.c
c/src/lib/libbsp/powerpc/papyrus/times
c/src/lib/libc/utsname.c
c/src/lib/libcpu/hppa1.1/clock/clock.c
c/src/lib/libcpu/hppa1.1/runway/runway.h
c/src/lib/libcpu/hppa1.1/semaphore/semaphore.c
c/src/lib/libcpu/hppa1.1/semaphore/semaphore.h
c/src/lib/libcpu/hppa1.1/timer/timer.c
c/src/lib/libcpu/powerpc/README
c/src/lib/libcpu/powerpc/ppc403/README
c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
c/src/lib/libcpu/powerpc/ppc403/console/console.c
c/src/lib/libcpu/powerpc/ppc403/timer/timer.c
c/src/lib/libcpu/powerpc/ppc403/vectors/README
c/src/lib/libcpu/powerpc/ppc403/vectors/align_h.s
c/src/lib/libcpu/powerpc/ppc403/vectors/vectors.s
c/src/lib/libcpu/sparc/include/erc32.h
c/src/lib/libcpu/sparc/reg_win/window.s
c/src/libchip/shmdr/README
c/src/libchip/shmdr/addlq.c
c/src/libchip/shmdr/cnvpkt.c
c/src/libchip/shmdr/dump.c
c/src/libchip/shmdr/fatal.c
c/src/libchip/shmdr/getlq.c
c/src/libchip/shmdr/getpkt.c
c/src/libchip/shmdr/init.c
c/src/libchip/shmdr/initlq.c
c/src/libchip/shmdr/intr.c
c/src/libchip/shmdr/mpci.h
c/src/libchip/shmdr/mpisr.c
c/src/libchip/shmdr/poll.c
c/src/libchip/shmdr/receive.c
c/src/libchip/shmdr/retpkt.c
c/src/libchip/shmdr/send.c
c/src/libchip/shmdr/setckvec.c
c/src/libchip/shmdr/shm_driver.h
c/src/optman/rtems/no-dpmem.c
c/src/optman/rtems/no-event.c
c/src/optman/rtems/no-mp.c
c/src/optman/rtems/no-msg.c
c/src/optman/rtems/no-part.c
c/src/optman/rtems/no-region.c
c/src/optman/rtems/no-rtmon.c
c/src/optman/rtems/no-sem.c
c/src/optman/rtems/no-signal.c
c/src/optman/rtems/no-timer.c
c/src/optman/sapi/no-ext.c
c/src/optman/sapi/no-io.c
cpukit/libcsupport/include/clockdrv.h
cpukit/libcsupport/include/console.h
cpukit/libcsupport/include/iosupp.h
cpukit/libcsupport/include/ringbuf.h
cpukit/libcsupport/include/rtems/assoc.h
cpukit/libcsupport/include/rtems/error.h
cpukit/libcsupport/include/rtems/libcsupport.h
cpukit/libcsupport/include/rtems/libio.h
cpukit/libcsupport/include/spurious.h
cpukit/libcsupport/include/sys/utsname.h
cpukit/libcsupport/include/timerdrv.h
cpukit/libcsupport/include/vmeintr.h
cpukit/libcsupport/src/README
cpukit/libcsupport/src/__brk.c
cpukit/libcsupport/src/__gettod.c
cpukit/libcsupport/src/__times.c
cpukit/libcsupport/src/assoc.c
cpukit/libcsupport/src/error.c
cpukit/libcsupport/src/hosterr.c
cpukit/libcsupport/src/libio.c
cpukit/libcsupport/src/malloc.c
cpukit/libcsupport/src/newlibc.c
cpukit/libcsupport/src/no_libc.c
cpukit/libcsupport/src/unixlibc.c
cpukit/libcsupport/src/utsname.c
cpukit/libmisc/README
cpukit/libmisc/monitor/README
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cpukit/libmisc/monitor/mon-config.c
cpukit/libmisc/monitor/mon-dname.c
cpukit/libmisc/monitor/mon-driver.c
cpukit/libmisc/monitor/mon-extension.c
cpukit/libmisc/monitor/mon-itask.c
cpukit/libmisc/monitor/mon-manager.c
cpukit/libmisc/monitor/mon-monitor.c
cpukit/libmisc/monitor/mon-mpci.c
cpukit/libmisc/monitor/mon-object.c
cpukit/libmisc/monitor/mon-prmisc.c
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cpukit/libmisc/monitor/mon-server.c
cpukit/libmisc/monitor/mon-symbols.c
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cpukit/libmisc/stackchk/README
cpukit/libmisc/stackchk/check.c
cpukit/libmisc/stackchk/internal.h
cpukit/libmisc/stackchk/stackchk.h
cpukit/posix/include/aio.h
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cpukit/posix/src/psignal.c
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cpukit/posix/src/sched.c
cpukit/posix/src/semaphore.c
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cpukit/posix/src/types.c
cpukit/rtems/include/rtems.h
cpukit/rtems/include/rtems/rtems/asr.h
cpukit/rtems/include/rtems/rtems/attr.h
cpukit/rtems/include/rtems/rtems/clock.h
cpukit/rtems/include/rtems/rtems/dpmem.h
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cpukit/rtems/include/rtems/rtems/eventmp.h
cpukit/rtems/include/rtems/rtems/eventset.h
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cpukit/rtems/include/rtems/rtems/message.h
cpukit/rtems/include/rtems/rtems/modes.h
cpukit/rtems/include/rtems/rtems/mp.h
cpukit/rtems/include/rtems/rtems/msgmp.h
cpukit/rtems/include/rtems/rtems/options.h
cpukit/rtems/include/rtems/rtems/part.h
cpukit/rtems/include/rtems/rtems/partmp.h
cpukit/rtems/include/rtems/rtems/ratemon.h
cpukit/rtems/include/rtems/rtems/region.h
cpukit/rtems/include/rtems/rtems/regionmp.h
cpukit/rtems/include/rtems/rtems/rtemsapi.h
cpukit/rtems/include/rtems/rtems/sem.h
cpukit/rtems/include/rtems/rtems/semmp.h
cpukit/rtems/include/rtems/rtems/signal.h
cpukit/rtems/include/rtems/rtems/signalmp.h
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cpukit/rtems/include/rtems/rtems/timer.h
cpukit/rtems/include/rtems/rtems/types.h
cpukit/rtems/inline/rtems/rtems/asr.inl
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cpukit/rtems/inline/rtems/rtems/dpmem.inl
cpukit/rtems/inline/rtems/rtems/event.inl
cpukit/rtems/inline/rtems/rtems/eventset.inl
cpukit/rtems/inline/rtems/rtems/message.inl
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cpukit/rtems/inline/rtems/rtems/options.inl
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cpukit/rtems/inline/rtems/rtems/ratemon.inl
cpukit/rtems/inline/rtems/rtems/region.inl
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cpukit/rtems/macros/rtems/rtems/asr.inl
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cpukit/rtems/macros/rtems/rtems/dpmem.inl
cpukit/rtems/macros/rtems/rtems/event.inl
cpukit/rtems/macros/rtems/rtems/eventset.inl
cpukit/rtems/macros/rtems/rtems/message.inl
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cpukit/rtems/macros/rtems/rtems/options.inl
cpukit/rtems/macros/rtems/rtems/part.inl
cpukit/rtems/macros/rtems/rtems/ratemon.inl
cpukit/rtems/macros/rtems/rtems/region.inl
cpukit/rtems/macros/rtems/rtems/sem.inl
cpukit/rtems/macros/rtems/rtems/status.inl
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cpukit/rtems/macros/rtems/rtems/tasks.inl
cpukit/rtems/macros/rtems/rtems/timer.inl
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cpukit/rtems/src/eventmp.c
cpukit/rtems/src/intr.c
cpukit/rtems/src/mp.c
cpukit/rtems/src/msg.c
cpukit/rtems/src/msgmp.c
cpukit/rtems/src/part.c
cpukit/rtems/src/partmp.c
cpukit/rtems/src/ratemon.c
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cpukit/rtems/src/regionmp.c
cpukit/rtems/src/rtclock.c
cpukit/rtems/src/rtemstimer.c
cpukit/rtems/src/sem.c
cpukit/rtems/src/semmp.c
cpukit/rtems/src/signal.c
cpukit/rtems/src/signalmp.c
cpukit/rtems/src/taskmp.c
cpukit/rtems/src/tasks.c
cpukit/sapi/include/confdefs.h
cpukit/sapi/include/rtems/config.h
cpukit/sapi/include/rtems/extension.h
cpukit/sapi/include/rtems/fatal.h
cpukit/sapi/include/rtems/init.h
cpukit/sapi/include/rtems/io.h
cpukit/sapi/include/rtems/mptables.h
cpukit/sapi/inline/rtems/extension.inl
cpukit/sapi/macros/rtems/extension.inl
cpukit/sapi/src/debug.c
cpukit/sapi/src/exinit.c
cpukit/sapi/src/extension.c
cpukit/sapi/src/fatal.c
cpukit/sapi/src/io.c
cpukit/sapi/src/rtemsapi.c
cpukit/score/cpu/hppa1.1/cpu.c
cpukit/score/cpu/i386/asm.h
cpukit/score/cpu/i386/cpu.c
cpukit/score/cpu/i386/rtems/asm.h
cpukit/score/cpu/i960/asm.h
cpukit/score/cpu/i960/cpu.c
cpukit/score/cpu/m68k/asm.h
cpukit/score/cpu/m68k/cpu.c
cpukit/score/cpu/m68k/m68302.h
cpukit/score/cpu/m68k/qsm.h
cpukit/score/cpu/m68k/rtems/asm.h
cpukit/score/cpu/m68k/rtems/m68k/m68302.h
cpukit/score/cpu/m68k/rtems/m68k/qsm.h
cpukit/score/cpu/m68k/rtems/m68k/sim.h
cpukit/score/cpu/m68k/sim.h
cpukit/score/cpu/no_cpu/asm.h
cpukit/score/cpu/no_cpu/cpu.c
cpukit/score/cpu/no_cpu/cpu_asm.c
cpukit/score/cpu/no_cpu/rtems/asm.h
cpukit/score/cpu/sparc/README
cpukit/score/cpu/sparc/asm.h
cpukit/score/cpu/sparc/cpu.c
cpukit/score/cpu/sparc/rtems/asm.h
cpukit/score/cpu/unix/cpu.c
cpukit/score/include/rtems/debug.h
cpukit/score/include/rtems/score/address.h
cpukit/score/include/rtems/score/apiext.h
cpukit/score/include/rtems/score/bitfield.h
cpukit/score/include/rtems/score/chain.h
cpukit/score/include/rtems/score/context.h
cpukit/score/include/rtems/score/copyrt.h
cpukit/score/include/rtems/score/coremsg.h
cpukit/score/include/rtems/score/coremutex.h
cpukit/score/include/rtems/score/coresem.h
cpukit/score/include/rtems/score/heap.h
cpukit/score/include/rtems/score/interr.h
cpukit/score/include/rtems/score/isr.h
cpukit/score/include/rtems/score/mpci.h
cpukit/score/include/rtems/score/mppkt.h
cpukit/score/include/rtems/score/object.h
cpukit/score/include/rtems/score/objectmp.h
cpukit/score/include/rtems/score/priority.h
cpukit/score/include/rtems/score/stack.h
cpukit/score/include/rtems/score/states.h
cpukit/score/include/rtems/score/sysstate.h
cpukit/score/include/rtems/score/thread.h
cpukit/score/include/rtems/score/threadmp.h
cpukit/score/include/rtems/score/threadq.h
cpukit/score/include/rtems/score/tod.h
cpukit/score/include/rtems/score/tqdata.h
cpukit/score/include/rtems/score/userext.h
cpukit/score/include/rtems/score/watchdog.h
cpukit/score/include/rtems/score/wkspace.h
cpukit/score/include/rtems/system.h
cpukit/score/inline/rtems/score/address.inl
cpukit/score/inline/rtems/score/chain.inl
cpukit/score/inline/rtems/score/coremsg.inl
cpukit/score/inline/rtems/score/coremutex.inl
cpukit/score/inline/rtems/score/coresem.inl
cpukit/score/inline/rtems/score/heap.inl
cpukit/score/inline/rtems/score/isr.inl
cpukit/score/inline/rtems/score/mppkt.inl
cpukit/score/inline/rtems/score/object.inl
cpukit/score/inline/rtems/score/objectmp.inl
cpukit/score/inline/rtems/score/priority.inl
cpukit/score/inline/rtems/score/stack.inl
cpukit/score/inline/rtems/score/states.inl
cpukit/score/inline/rtems/score/sysstate.inl
cpukit/score/inline/rtems/score/thread.inl
cpukit/score/inline/rtems/score/threadmp.inl
cpukit/score/inline/rtems/score/tod.inl
cpukit/score/inline/rtems/score/tqdata.inl
cpukit/score/inline/rtems/score/userext.inl
cpukit/score/inline/rtems/score/watchdog.inl
cpukit/score/inline/rtems/score/wkspace.inl
cpukit/score/macros/README
cpukit/score/macros/rtems/score/README
cpukit/score/macros/rtems/score/address.inl
cpukit/score/macros/rtems/score/chain.inl
cpukit/score/macros/rtems/score/coremsg.inl
cpukit/score/macros/rtems/score/coremutex.inl
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cpukit/score/macros/rtems/score/heap.inl
cpukit/score/macros/rtems/score/isr.inl
cpukit/score/macros/rtems/score/mppkt.inl
cpukit/score/macros/rtems/score/object.inl
cpukit/score/macros/rtems/score/objectmp.inl
cpukit/score/macros/rtems/score/priority.inl
cpukit/score/macros/rtems/score/stack.inl
cpukit/score/macros/rtems/score/states.inl
cpukit/score/macros/rtems/score/sysstate.inl
cpukit/score/macros/rtems/score/thread.inl
cpukit/score/macros/rtems/score/threadmp.inl
cpukit/score/macros/rtems/score/tod.inl
cpukit/score/macros/rtems/score/tqdata.inl
cpukit/score/macros/rtems/score/userext.inl
cpukit/score/macros/rtems/score/watchdog.inl
cpukit/score/macros/rtems/score/wkspace.inl
cpukit/score/src/apiext.c
cpukit/score/src/chain.c
cpukit/score/src/coremsg.c
cpukit/score/src/coremutex.c
cpukit/score/src/coresem.c
cpukit/score/src/coretod.c
cpukit/score/src/heap.c
cpukit/score/src/interr.c
cpukit/score/src/isr.c
cpukit/score/src/mpci.c
cpukit/score/src/object.c
cpukit/score/src/objectmp.c
cpukit/score/src/thread.c
cpukit/score/src/threadmp.c
cpukit/score/src/threadq.c
cpukit/score/src/userext.c
cpukit/score/src/watchdog.c
cpukit/score/src/wkspace.c
testsuites/README
testsuites/libtests/README
testsuites/libtests/stackchk/blow.c
testsuites/libtests/stackchk/init.c
testsuites/libtests/stackchk/stackchk.scn
testsuites/libtests/stackchk/system.h
testsuites/libtests/stackchk/task1.c
testsuites/mptests/README
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testsuites/mptests/mp01/node1/mp01.doc
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testsuites/mptests/mp10/init.c
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testsuites/mptests/mp13/task2.c
testsuites/mptests/mp14/delay.c
testsuites/mptests/mp14/evtask1.c
testsuites/mptests/mp14/evtmtask.c
testsuites/mptests/mp14/exit.c
testsuites/mptests/mp14/init.c
testsuites/mptests/mp14/msgtask1.c
testsuites/mptests/mp14/node1/mp14.doc
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testsuites/mptests/mp14/pttask1.c
testsuites/mptests/mp14/smtask1.c
testsuites/mptests/mp14/system.h
testsuites/samples/README
testsuites/samples/base_mp/apptask.c
testsuites/samples/base_mp/init.c
testsuites/samples/base_mp/node1/base_mp.doc
testsuites/samples/base_mp/node1/base_mp.scn
testsuites/samples/base_mp/node2/base_mp.doc
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testsuites/samples/base_sp/apptask.c
testsuites/samples/base_sp/base_sp.doc
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testsuites/samples/base_sp/system.h
testsuites/samples/cdtest/cdtest.scn
testsuites/samples/cdtest/init.c
testsuites/samples/cdtest/main.cc
testsuites/samples/cdtest/system.h
testsuites/samples/hello/hello.doc
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testsuites/samples/hello/init.c
testsuites/samples/hello/system.h
testsuites/samples/paranoia/init.c
testsuites/samples/paranoia/paranoia.c
testsuites/samples/paranoia/paranoia.doc
testsuites/samples/paranoia/system.h
testsuites/samples/ticker/init.c
testsuites/samples/ticker/system.h
testsuites/samples/ticker/tasks.c
testsuites/samples/ticker/ticker.doc
testsuites/samples/ticker/ticker.scn
testsuites/sptests/README
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testsuites/sptests/sp01/sp01.doc
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testsuites/sptests/sp01/task1.c
testsuites/sptests/sp02/init.c
testsuites/sptests/sp02/preempt.c
testsuites/sptests/sp02/sp02.doc
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testsuites/sptests/sp02/task1.c
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testsuites/sptests/sp02/task3.c
testsuites/sptests/sp03/init.c
testsuites/sptests/sp03/sp03.doc
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testsuites/sptests/sp03/task1.c
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testsuites/sptests/sp04/init.c
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testsuites/sptests/sp04/task1.c
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testsuites/sptests/sp04/task3.c
testsuites/sptests/sp04/tswitch.c
testsuites/sptests/sp05/init.c
testsuites/sptests/sp05/sp05.doc
testsuites/sptests/sp05/sp05.scn
testsuites/sptests/sp05/system.h
testsuites/sptests/sp05/task1.c
testsuites/sptests/sp05/task2.c
testsuites/sptests/sp05/task3.c
testsuites/sptests/sp06/init.c
testsuites/sptests/sp06/sp06.doc
testsuites/sptests/sp06/sp06.scn
testsuites/sptests/sp06/system.h
testsuites/sptests/sp06/task1.c
testsuites/sptests/sp06/task2.c
testsuites/sptests/sp06/task3.c
testsuites/sptests/sp07/init.c
testsuites/sptests/sp07/sp07.doc
testsuites/sptests/sp07/sp07.scn
testsuites/sptests/sp07/system.h
testsuites/sptests/sp07/task1.c
testsuites/sptests/sp07/task2.c
testsuites/sptests/sp07/task3.c
testsuites/sptests/sp07/task4.c
testsuites/sptests/sp07/taskexit.c
testsuites/sptests/sp07/tcreate.c
testsuites/sptests/sp07/tdelete.c
testsuites/sptests/sp07/trestart.c
testsuites/sptests/sp07/tstart.c
testsuites/sptests/sp08/init.c
testsuites/sptests/sp08/sp08.doc
testsuites/sptests/sp08/sp08.scn
testsuites/sptests/sp08/system.h
testsuites/sptests/sp08/task1.c
testsuites/sptests/sp09/delay.c
testsuites/sptests/sp09/init.c
testsuites/sptests/sp09/isr.c
testsuites/sptests/sp09/screen01.c
testsuites/sptests/sp09/screen02.c
testsuites/sptests/sp09/screen03.c
testsuites/sptests/sp09/screen04.c
testsuites/sptests/sp09/screen05.c
testsuites/sptests/sp09/screen06.c
testsuites/sptests/sp09/screen07.c
testsuites/sptests/sp09/screen08.c
testsuites/sptests/sp09/screen09.c
testsuites/sptests/sp09/screen10.c
testsuites/sptests/sp09/screen11.c
testsuites/sptests/sp09/screen12.c
testsuites/sptests/sp09/screen13.c
testsuites/sptests/sp09/screen14.c
testsuites/sptests/sp09/sp09.doc
testsuites/sptests/sp09/sp09.scn
testsuites/sptests/sp09/system.h
testsuites/sptests/sp09/task1.c
testsuites/sptests/sp09/task2.c
testsuites/sptests/sp09/task3.c
testsuites/sptests/sp09/task4.c
testsuites/sptests/sp11/init.c
testsuites/sptests/sp11/sp11.doc
testsuites/sptests/sp11/sp11.scn
testsuites/sptests/sp11/system.h
testsuites/sptests/sp11/task1.c
testsuites/sptests/sp11/task2.c
testsuites/sptests/sp11/timer.c
testsuites/sptests/sp12/init.c
testsuites/sptests/sp12/pridrv.c
testsuites/sptests/sp12/pritask.c
testsuites/sptests/sp12/sp12.doc
testsuites/sptests/sp12/sp12.scn
testsuites/sptests/sp12/system.h
testsuites/sptests/sp12/task1.c
testsuites/sptests/sp12/task2.c
testsuites/sptests/sp12/task3.c
testsuites/sptests/sp12/task4.c
testsuites/sptests/sp12/task5.c
testsuites/sptests/sp13/fillbuff.c
testsuites/sptests/sp13/init.c
testsuites/sptests/sp13/putbuff.c
testsuites/sptests/sp13/sp13.doc
testsuites/sptests/sp13/sp13.scn
testsuites/sptests/sp13/system.h
testsuites/sptests/sp13/task1.c
testsuites/sptests/sp13/task2.c
testsuites/sptests/sp13/task3.c
testsuites/sptests/sp14/asr.c
testsuites/sptests/sp14/init.c
testsuites/sptests/sp14/sp14.doc
testsuites/sptests/sp14/sp14.scn
testsuites/sptests/sp14/system.h
testsuites/sptests/sp14/task1.c
testsuites/sptests/sp14/task2.c
testsuites/sptests/sp15/init.c
testsuites/sptests/sp15/sp15.doc
testsuites/sptests/sp15/sp15.scn
testsuites/sptests/sp15/system.h
testsuites/sptests/sp15/task1.c
testsuites/sptests/sp16/init.c
testsuites/sptests/sp16/sp16.doc
testsuites/sptests/sp16/sp16.scn
testsuites/sptests/sp16/system.h
testsuites/sptests/sp16/task1.c
testsuites/sptests/sp16/task2.c
testsuites/sptests/sp16/task3.c
testsuites/sptests/sp16/task4.c
testsuites/sptests/sp16/task5.c
testsuites/sptests/sp17/asr.c
testsuites/sptests/sp17/init.c
testsuites/sptests/sp17/sp17.doc
testsuites/sptests/sp17/sp17.scn
testsuites/sptests/sp17/system.h
testsuites/sptests/sp17/task1.c
testsuites/sptests/sp17/task2.c
testsuites/sptests/sp19/first.c
testsuites/sptests/sp19/fptask.c
testsuites/sptests/sp19/fptest.h
testsuites/sptests/sp19/init.c
testsuites/sptests/sp19/inttest.h
testsuites/sptests/sp19/sp19.doc
testsuites/sptests/sp19/sp19.scn
testsuites/sptests/sp19/system.h
testsuites/sptests/sp19/task1.c
testsuites/sptests/sp20/getall.c
testsuites/sptests/sp20/init.c
testsuites/sptests/sp20/sp20.doc
testsuites/sptests/sp20/sp20.scn
testsuites/sptests/sp20/system.h
testsuites/sptests/sp20/task1.c
testsuites/sptests/sp21/init.c
testsuites/sptests/sp21/sp21.doc
testsuites/sptests/sp21/sp21.scn
testsuites/sptests/sp21/system.h
testsuites/sptests/sp21/task1.c
testsuites/sptests/sp22/delay.c
testsuites/sptests/sp22/init.c
testsuites/sptests/sp22/prtime.c
testsuites/sptests/sp22/sp22.doc
testsuites/sptests/sp22/sp22.scn
testsuites/sptests/sp22/system.h
testsuites/sptests/sp22/task1.c
testsuites/sptests/sp23/init.c
testsuites/sptests/sp23/sp23.doc
testsuites/sptests/sp23/sp23.scn
testsuites/sptests/sp23/system.h
testsuites/sptests/sp23/task1.c
testsuites/sptests/sp24/init.c
testsuites/sptests/sp24/resume.c
testsuites/sptests/sp24/sp24.doc
testsuites/sptests/sp24/sp24.scn
testsuites/sptests/sp24/system.h
testsuites/sptests/sp24/task1.c
testsuites/sptests/sp25/init.c
testsuites/sptests/sp25/sp25.doc
testsuites/sptests/sp25/sp25.scn
testsuites/sptests/sp25/system.h
testsuites/sptests/sp25/task1.c
testsuites/sptests/spfatal/fatal.c
testsuites/sptests/spfatal/init.c
testsuites/sptests/spfatal/puterr.c
testsuites/sptests/spfatal/spfatal.doc
testsuites/sptests/spfatal/spfatal.scn
testsuites/sptests/spfatal/system.h
testsuites/sptests/spfatal/task1.c
testsuites/sptests/spsize/getint.c
testsuites/sptests/spsize/init.c
testsuites/sptests/spsize/size.c
testsuites/sptests/spsize/system.h
testsuites/support/include/tmacros.h
testsuites/tmtests/README
testsuites/tmtests/include/timesys.h
testsuites/tmtests/tm01/system.h
testsuites/tmtests/tm01/task1.c
testsuites/tmtests/tm01/tm01.doc
testsuites/tmtests/tm02/system.h
testsuites/tmtests/tm02/task1.c
testsuites/tmtests/tm02/tm02.doc
testsuites/tmtests/tm03/system.h
testsuites/tmtests/tm03/task1.c
testsuites/tmtests/tm03/tm03.doc
testsuites/tmtests/tm04/system.h
testsuites/tmtests/tm04/task1.c
testsuites/tmtests/tm04/tm04.doc
testsuites/tmtests/tm05/system.h
testsuites/tmtests/tm05/task1.c
testsuites/tmtests/tm05/tm05.doc
testsuites/tmtests/tm06/system.h
testsuites/tmtests/tm06/task1.c
testsuites/tmtests/tm06/tm06.doc
testsuites/tmtests/tm07/system.h
testsuites/tmtests/tm07/task1.c
testsuites/tmtests/tm07/tm07.doc
testsuites/tmtests/tm08/system.h
testsuites/tmtests/tm08/task1.c
testsuites/tmtests/tm08/tm08.doc
testsuites/tmtests/tm09/system.h
testsuites/tmtests/tm09/task1.c
testsuites/tmtests/tm09/tm09.doc
testsuites/tmtests/tm10/system.h
testsuites/tmtests/tm10/task1.c
testsuites/tmtests/tm10/tm10.doc
testsuites/tmtests/tm11/system.h
testsuites/tmtests/tm11/task1.c
testsuites/tmtests/tm11/tm11.doc
testsuites/tmtests/tm12/system.h
testsuites/tmtests/tm12/task1.c
testsuites/tmtests/tm12/tm12.doc
testsuites/tmtests/tm13/system.h
testsuites/tmtests/tm13/task1.c
testsuites/tmtests/tm13/tm13.doc
testsuites/tmtests/tm14/system.h
testsuites/tmtests/tm14/task1.c
testsuites/tmtests/tm14/tm14.doc
testsuites/tmtests/tm15/system.h
testsuites/tmtests/tm15/task1.c
testsuites/tmtests/tm15/tm15.doc
testsuites/tmtests/tm16/system.h
testsuites/tmtests/tm16/task1.c
testsuites/tmtests/tm16/tm16.doc
testsuites/tmtests/tm17/system.h
testsuites/tmtests/tm17/task1.c
testsuites/tmtests/tm17/tm17.doc
testsuites/tmtests/tm18/system.h
testsuites/tmtests/tm18/task1.c
testsuites/tmtests/tm18/tm18.doc
testsuites/tmtests/tm19/system.h
testsuites/tmtests/tm19/task1.c
testsuites/tmtests/tm19/tm19.doc
testsuites/tmtests/tm20/system.h
testsuites/tmtests/tm20/task1.c
testsuites/tmtests/tm20/tm20.doc
testsuites/tmtests/tm21/system.h
testsuites/tmtests/tm21/task1.c
testsuites/tmtests/tm21/tm21.doc
testsuites/tmtests/tm22/system.h
testsuites/tmtests/tm22/task1.c
testsuites/tmtests/tm22/tm22.doc
testsuites/tmtests/tm23/system.h
testsuites/tmtests/tm23/task1.c
testsuites/tmtests/tm23/tm23.doc
testsuites/tmtests/tm24/system.h
testsuites/tmtests/tm24/task1.c
testsuites/tmtests/tm24/tm24.doc
testsuites/tmtests/tm25/system.h
testsuites/tmtests/tm25/task1.c
testsuites/tmtests/tm25/tm25.doc
testsuites/tmtests/tm26/fptest.h
testsuites/tmtests/tm26/system.h
testsuites/tmtests/tm26/task1.c
testsuites/tmtests/tm26/tm26.doc
testsuites/tmtests/tm27/system.h
testsuites/tmtests/tm27/task1.c
testsuites/tmtests/tm27/tm27.doc
testsuites/tmtests/tm28/system.h
testsuites/tmtests/tm28/task1.c
testsuites/tmtests/tm28/tm28.doc
testsuites/tmtests/tm29/system.h
testsuites/tmtests/tm29/task1.c
testsuites/tmtests/tm29/tm29.doc
testsuites/tmtests/tmck/system.h
testsuites/tmtests/tmck/task1.c
testsuites/tmtests/tmck/tmck.doc
testsuites/tmtests/tmoverhd/dumrtems.h
testsuites/tmtests/tmoverhd/empty.c
testsuites/tmtests/tmoverhd/system.h
testsuites/tmtests/tmoverhd/testtask.c
testsuites/tmtests/tmoverhd/tmoverhd.doc
tools/build/README
tools/build/cklength.c
tools/build/eolstrip.c
tools/build/os/msdos/README
tools/build/os/msdos/cklength.uue
tools/build/os/msdos/fixtimer.c
tools/build/os/msdos/fixtimer.uue
tools/build/os/msdos/ifc.c
tools/build/os/msdos/ifc_exe.uue
tools/build/packhex.c
tools/build/scripts/README
tools/build/src/cklength.c
tools/build/src/eolstrip.c
tools/build/src/packhex.c
tools/build/src/unhex.c
tools/build/unhex.c
tools/cpu/hppa1.1/genoffsets.c
tools/cpu/unix/gensize.c
tools/update/310_to_320_list
tools/update/README
Diffstat (limited to 'cpukit/score/cpu/m68k')
-rw-r--r-- | cpukit/score/cpu/m68k/asm.h | 127 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/cpu.c | 144 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/m68302.h | 608 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/qsm.h | 209 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/rtems/asm.h | 127 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/rtems/m68k/m68302.h | 608 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/rtems/m68k/qsm.h | 209 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/rtems/m68k/sim.h | 328 | ||||
-rw-r--r-- | cpukit/score/cpu/m68k/sim.h | 328 |
9 files changed, 0 insertions, 2688 deletions
diff --git a/cpukit/score/cpu/m68k/asm.h b/cpukit/score/cpu/m68k/asm.h deleted file mode 100644 index 4ce90c1b58..0000000000 --- a/cpukit/score/cpu/m68k/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __M68k_ASM_h -#define __M68k_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#define ASM -#include <rtems/score/m68k.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c deleted file mode 100644 index f57fae6685..0000000000 --- a/cpukit/score/cpu/m68k/cpu.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Motorola MC68xxx Dependent Source - * - * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. - * On-Line Applications Research Corporation (OAR). - * All rights assigned to U.S. Government, 1994. - * - * This material may be reproduced by or for the U.S. Government pursuant - * to the copyright license under the clause at DFARS 252.227-7013. This - * notice must appear in all copies of this file and its derivatives. - * - * $Id$ - */ - -#include <rtems/system.h> -#include <rtems/score/isr.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - entry pointer to thread dispatcher - * - * OUTPUT PARAMETERS: NONE - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - _CPU_Table = *cpu_table; -} - -/*PAGE - * - * _CPU_ISR_Get_level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 level; - - m68k_get_interrupt_level( level ); - - return level; -} - -/*PAGE - * - * _CPU_ISR_install_raw_handler - */ - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr *interrupt_table = NULL; - - m68k_get_vbr( interrupt_table ); - -#if ( M68K_HAS_VBR == 1) - *old_handler = interrupt_table[ vector ]; - interrupt_table[ vector ] = new_handler; -#else - *old_handler = *(proc_ptr *)( (int)interrupt_table+ (int)vector*6-10); - *(proc_ptr *)( (int)interrupt_table+ (int)vector*6-10) = new_handler; -#endif /* M68K_HAS_VBR */ -} - -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - former ISR for this vector number - * - * Output parameters: NONE - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - proc_ptr ignored; - - *old_handler = _ISR_Vector_table[ vector ]; - - _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); - - _ISR_Vector_table[ vector ] = new_handler; -} - - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -#if ( M68K_HAS_SEPARATE_STACKS == 1 ) - void *isp = _CPU_Interrupt_stack_high; - - asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) ); -#else -#warning "FIX ME... HOW DO I INSTALL THE INTERRUPT STACK!!!" -#endif -} - -#if ( M68K_HAS_BFFFO != 1 ) -/* - * Returns table for duplication of the BFFFO instruction (16 bits only) - */ -const unsigned char __BFFFOtable[256] = { - 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; -#endif diff --git a/cpukit/score/cpu/m68k/m68302.h b/cpukit/score/cpu/m68k/m68302.h deleted file mode 100644 index da96478cf3..0000000000 --- a/cpukit/score/cpu/m68k/m68302.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - *------------------------------------------------------------------ - * - * m68302.h - Definitions for Motorola MC68302 processor. - * - * Section references in this file refer to revision 2 of Motorola's - * "MC68302 Integrated Multiprotocol Processor User's Manual". - * (Motorola document MC68302UM/AD REV 2.) - * - * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k - * on 17 February, 1993. - * - * Copyright 1995 David W. Glessner. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above copyright notice, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - * - * $Id$ - * - *------------------------------------------------------------------ - */ - -#ifndef __MOTOROLA_MC68302_DEFINITIONS_h -#define __MOTOROLA_MC68302_DEFINITIONS_h - -/* - * BAR - Base Address Register - * Section 2.7 - */ -#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) - -/* - * SCR - System Control Register - * Section 3.8.1 - */ -#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) -/* - * SCR bits - */ -#define RBIT_SCR_IPA 0x08000000 -#define RBIT_SCR_HWT 0x04000000 -#define RBIT_SCR_WPV 0x02000000 -#define RBIT_SCR_ADC 0x01000000 - -#define RBIT_SCR_ERRE 0x00400000 -#define RBIT_SCR_VGE 0x00200000 -#define RBIT_SCR_WPVE 0x00100000 -#define RBIT_SCR_RMCST 0x00080000 -#define RBIT_SCR_EMWS 0x00040000 -#define RBIT_SCR_ADCE 0x00020000 -#define RBIT_SCR_BCLM 0x00010000 - -#define RBIT_SCR_FRZW 0x00008000 -#define RBIT_SCR_FRZ2 0x00004000 -#define RBIT_SCR_FRZ1 0x00002000 -#define RBIT_SCR_SAM 0x00001000 -#define RBIT_SCR_HWDEN 0x00000800 -#define RBIT_SCR_HWDCN2 0x00000400 -#define RBIT_SCR_HWDCN1 0x00000200 -#define RBIT_SCR_HWDCN0 0x00000100 - -#define RBIT_SCR_LPREC 0x00000080 -#define RBIT_SCR_LPP16 0x00000040 -#define RBIT_SCR_LPEN 0x00000020 -#define RBIT_SCR_LPCLKDIV 0x0000001f - - -/* - * 68000 interrupt and trap vector numbers - */ -#define M68K_IVEC_BUS_ERROR 2 -#define M68K_IVEC_ADDRESS_ERROR 3 -#define M68K_IVEC_ILLEGAL_OPCODE 4 -#define M68K_IVEC_ZERO_DIVIDE 5 -#define M68K_IVEC_CHK 6 -#define M68K_IVEC_TRAPV 7 -#define M68K_IVEC_PRIVILEGE 8 -#define M68K_IVEC_TRACE 9 -#define M68K_IVEC_LINE_A 10 -#define M68K_IVEC_LINE_F 11 -/* Unassigned, Reserved 12-14 */ -#define M68K_IVEC_UNINITIALIZED_INT 15 -/* Unassigned, Reserved 16-23 */ -#define M68K_IVEC_SPURIOUS_INT 24 - -#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 -#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 -#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 -#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 -#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 -#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 -#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 - -#define M68K_IVEC_TRAP0 32 -#define M68K_IVEC_TRAP1 33 -#define M68K_IVEC_TRAP2 34 -#define M68K_IVEC_TRAP3 35 -#define M68K_IVEC_TRAP4 36 -#define M68K_IVEC_TRAP5 37 -#define M68K_IVEC_TRAP6 38 -#define M68K_IVEC_TRAP7 39 -#define M68K_IVEC_TRAP8 40 -#define M68K_IVEC_TRAP9 41 -#define M68K_IVEC_TRAP10 42 -#define M68K_IVEC_TRAP11 43 -#define M68K_IVEC_TRAP12 44 -#define M68K_IVEC_TRAP13 45 -#define M68K_IVEC_TRAP14 46 -#define M68K_IVEC_TRAP15 47 -/* - * Unassigned, Reserved 48-59 - * - * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). - */ - -/* - * MC68302 Interrupt Vectors - * Section 3.2 - */ -enum m68302_ivec_e { - M302_IVEC_ERR =0, - M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ - M302_IVEC_SMC2 =2, - M302_IVEC_SMC1 =3, - M302_IVEC_TIMER3 =4, - M302_IVEC_SCP =5, - M302_IVEC_TIMER2 =6, - M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ - M302_IVEC_SCC3 =8, - M302_IVEC_TIMER1 =9, - M302_IVEC_SCC2 =10, - M302_IVEC_IDMA =11, - M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ - M302_IVEC_SCC1 =13, - M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ - M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ - M302_IVEC_IRQ1 =17, /* External Device */ - M302_IVEC_IRQ6 =22, /* External Device */ - M302_IVEC_IRQ7 =23 /* External Device */ -}; - - -/* - * GIMR - Global Interrupt Mode Register - * Section 3.2.5.1 - */ -#define RBIT_GIMR_MOD (1<<15) -#define RBIT_GIMR_IV7 (1<<14) -#define RBIT_GIMR_IV6 (1<<13) -#define RBIT_GIMR_IV1 (1<<12) -#define RBIT_GIMR_ET7 (1<<10) -#define RBIT_GIMR_ET6 (1<<9) -#define RBIT_GIMR_ET1 (1<<8) -#define RBIT_GIMR_VECTOR (7<<5) - -/* - * IPR - Interrupt Pending Register (Section 3.2.5.2) - * IMR - Interrupt Mask Register (Section 3.2.5.3) - * ISR - Interrupt In-Service Register (Section 3.2.5.4) - */ -#define RBIT_IPR_PB11 (1<<15) -#define RBIT_IPR_PB10 (1<<14) -#define RBIT_IPR_SCC1 (1<<13) -#define RBIT_IPR_SDMA (1<<12) -#define RBIT_IPR_IDMA (1<<11) -#define RBIT_IPR_SCC2 (1<<10) -#define RBIT_IPR_TIMER1 (1<<9) -#define RBIT_IPR_SCC3 (1<<8) -#define RBIT_IPR_PB9 (1<<7) -#define RBIT_IPR_TIMER2 (1<<6) -#define RBIT_IPR_SCP (1<<5) -#define RBIT_IPR_TIMER3 (1<<4) -#define RBIT_IPR_SMC1 (1<<3) -#define RBIT_IPR_SMC2 (1<<2) -#define RBIT_IPR_PB8 (1<<1) -#define RBIT_IPR_ERR (1<<0) - -#define RBIT_ISR_PB11 (1<<15) -#define RBIT_ISR_PB10 (1<<14) -#define RBIT_ISR_SCC1 (1<<13) -#define RBIT_ISR_SDMA (1<<12) -#define RBIT_ISR_IDMA (1<<11) -#define RBIT_ISR_SCC2 (1<<10) -#define RBIT_ISR_TIMER1 (1<<9) -#define RBIT_ISR_SCC3 (1<<8) -#define RBIT_ISR_PB9 (1<<7) -#define RBIT_ISR_TIMER2 (1<<6) -#define RBIT_ISR_SCP (1<<5) -#define RBIT_ISR_TIMER3 (1<<4) -#define RBIT_ISR_SMC1 (1<<3) -#define RBIT_ISR_SMC2 (1<<2) -#define RBIT_ISR_PB8 (1<<1) - -#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ -#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ -#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ -#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ -#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ -#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ -#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ -#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ -#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ -#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ -#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ -#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ -#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ -#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ -#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ - - -/* - * DRAM Refresh - * Section 3.9 - * - * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 - * structures in the parameter RAM. - * - * Access to the DRAM registers can be accomplished by - * the following approach: - * - * volatile m302_DRAM_refresh_t *dram; - * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; - * - * Then simply use pointer references (e.g. dram->count = 3). - */ -typedef struct { - rtems_unsigned16 dram_high; /* DRAM high address and FC */ - rtems_unsigned16 dram_low; /* DRAM low address */ - rtems_unsigned16 increment; /* increment step (bytes/row) */ - rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ - rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ - rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ - rtems_unsigned16 t_count; /* temporary refresh cycles count */ - rtems_unsigned16 res; /* reserved */ -} m302_DRAM_refresh_t; - - -/* - * TMR - Timer Mode Register (for timers 1 and 2) - * Section 3.5.2.1 - */ -#define RBIT_TMR_ICLK_STOP (0<<1) -#define RBIT_TMR_ICLK_MASTER (1<<1) -#define RBIT_TMR_ICLK_MASTER16 (2<<1) -#define RBIT_TMR_ICLK_TIN (3<<1) - -#define RBIT_TMR_OM (1<<5) -#define RBIT_TMR_ORI (1<<4) -#define RBIT_TMR_FRR (1<<3) -#define RBIT_TMR_RST (1<<0) - - -/* - * TER - Timer Event Register (for timers 1 and 2) - * Section 3.5.2.5 - */ -#define RBIT_TER_REF (1<<1) /* Output Reference Event */ -#define RBIT_TER_CAP (1<<0) /* Capture Event */ - - -/* - * SCC Buffer Descriptors and Buffer Descriptors Table - * Section 4.5.5 - */ -typedef struct m302_SCC_bd { - rtems_unsigned16 status; /* status and control */ - rtems_unsigned16 length; /* data length */ - rtems_unsigned8 *buffer; /* data buffer pointer */ -} m302_SCC_bd_t; - -typedef struct { - m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ - m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ -} m302_SCC_bd_table_t; - - -/* - * SCC Parameter RAM (offset 0x080 from an SCC Base) - * Section 4.5.6 - * - * Each SCC parameter RAM area begins at offset 0x80 from each SCC base - * area (0x400, 0x500, or 0x600 from the dual-port RAM base). - * - * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific - * portion of the SCC parameter RAM. - */ -typedef struct { - rtems_unsigned8 rfcr; /* Rx Function Code */ - rtems_unsigned8 tfcr; /* Tx Function Code */ - rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ - rtems_unsigned16 _rstate; /* Rx Internal State */ - rtems_unsigned8 res2; - rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ - rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ - rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ - rtems_unsigned16 _rtmp; /* Rx Temp */ - rtems_unsigned16 _tstate; /* Tx Internal State */ - rtems_unsigned8 res7; - rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ - rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ - rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ - rtems_unsigned16 _ttmp; /* Tx Temp */ -} m302_SCC_parameters_t; - -/* - * UART-Specific SCC Parameter RAM - * Section 4.5.11.3 - */ -typedef struct { - rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ - rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ - rtems_unsigned16 brkcr; /* Break Count Register (tx) */ - rtems_unsigned16 parec; /* Receive Parity Error Counter */ - rtems_unsigned16 frmec; /* Receive Framing Error Counter */ - rtems_unsigned16 nosec; /* Receive Noise Counter */ - rtems_unsigned16 brkec; /* Receive Break Condition Counter */ - rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ - rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ - rtems_unsigned16 rccr; /* Receive Control Character Register */ - rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ -} m302_SCC_UartSpecific_t; -/* - * This definition allows for the checking of receive buffers - * for errors. - */ - -#define RCV_ERR 0x003F - -/* - * UART receive buffer descriptor bit definitions. - * Section 4.5.11.14 - */ -#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ -#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ -#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ -#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ -#define RBIT_UART_BR (1<<5) /* break sequence was received */ -#define RBIT_UART_FR (1<<4) /* framing error was received */ -#define RBIT_UART_PR (1<<3) /* parity error was received */ -#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ -#define RBIT_UART_CD (1<<0) /* carrier detect lost */ -#define RBIT_UART_STATUS 0x003B /* all status bits */ - -/* - * UART transmit buffer descriptor bit definitions. - * Section 4.5.11.15 - */ -#define RBIT_UART_CR (1<<11) /* clear-to-send report - * this results in two idle bits - * between back-to-back frames - */ -#define RBIT_UART_A (1<<10) /* buffer contains address characters - * only valid in multidrop mode (UM0=1) - */ -#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ -#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ - -/* - * UART event register - * Section 4.5.11.16 - */ -#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ -#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ -#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ -#define M302_UART_EV_BRK (1<<4) /* break character was received */ -#define M302_UART_EV_CCR (1<<3) /* control character received */ -#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ -#define M302_UART_EV_RX (1<<0) /* buffer has been received */ - - -/* - * HDLC-Specific SCC Parameter RAM - * Section 4.5.12.3 - * - * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC - * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC - */ -typedef struct { - rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ - rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ - rtems_unsigned16 c_mask_l; /* CRC Mask Low */ - rtems_unsigned16 c_mask_h; /* CRC Mask High */ - rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ - rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ - - rtems_unsigned16 disfc; /* Discard Frame Counter */ - rtems_unsigned16 crcec; /* CRC Error Counter */ - rtems_unsigned16 abtsc; /* Abort Sequence Counter */ - rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ - rtems_unsigned16 retrc; /* Frame Retransmission Counter */ - - rtems_unsigned16 mflr; /* Maximum Frame Length Register */ - rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ - - rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ - rtems_unsigned16 haddr1; /* User Defined Frame Address */ - rtems_unsigned16 haddr2; /* " */ - rtems_unsigned16 haddr3; /* " */ - rtems_unsigned16 haddr4; /* " */ -} m302_SCC_HdlcSpecific_t; -/* - * HDLC receiver buffer descriptor bit definitions - * Section 4.5.12.10 - */ -#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ -#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ -#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ -#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ -#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ -#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ -#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ -#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ - -/* - * HDLC transmit buffer descriptor bit definitions - * Section 4.5.12.11 - */ -#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ -#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ -#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ -#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ -#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ -#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ -#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ - -/* - * HDLC event register bit definitions - * Section 4.5.12.12 - */ -#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ -#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ -#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ -#define RBIT_HDLC_TXE 0x10 /* transmit error */ -#define RBIT_HDLC_RXF 0x08 /* received frame */ -#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to - * lack of buffers - */ -#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ -#define RBIT_HDLC_RXB 0x01 /* received buffer */ - - - -typedef struct { - m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ - m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ - union { /* +09C Protocol-Specific Parm RAM */ - m302_SCC_UartSpecific_t uart; - m302_SCC_HdlcSpecific_t hdlc; - } prot; - rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ -} m302_SCC_t; - - -/* - * Common SCC Registers - */ -typedef struct { - rtems_unsigned16 res1; - rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ - rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ - rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ - rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ - rtems_unsigned8 res2; - rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ - rtems_unsigned8 res3; - rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ - rtems_unsigned8 res4; - rtems_unsigned16 res5; -} m302_SCC_Registers_t; - -/* - * SCON - SCC Configuration Register - * Section 4.5.2 - */ -#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) - * When set, the TXD driver is an - * open-drain output */ -#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ -#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ -#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ - -/* - * SCM - SCC Mode Register bit definitions - * Section 4.5.3 - * The parameter-specific mode bits occupy bits 15 through 6. - */ -#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ -#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ - - -/* - * Internal MC68302 Registers - * starts at offset 0x800 from dual-port RAM base - * Section 2.8 - */ -typedef struct { - /* offset +800 */ - rtems_unsigned16 res0; - rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ - rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ - rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ - rtems_unsigned16 bcr; /* IDMA Byte Count Register */ - rtems_unsigned8 csr; /* IDMA Channel Status Register */ - rtems_unsigned8 res1; - rtems_unsigned8 fcr; /* IDMA Function Code Register */ - rtems_unsigned8 res2; - - /* offset +812 */ - rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ - rtems_unsigned16 ipr; /* Interrupt Pending Register */ - rtems_unsigned16 imr; /* Interrupt Mask Register */ - rtems_unsigned16 isr; /* Interrupt In-Service Register */ - rtems_unsigned16 res3; - rtems_unsigned16 res4; - - /* offset +81e */ - rtems_unsigned16 pacnt; /* Port A Control Register */ - rtems_unsigned16 paddr; /* Port A Data Direction Register */ - rtems_unsigned16 padat; /* Port A Data Register */ - rtems_unsigned16 pbcnt; /* Port B Control Register */ - rtems_unsigned16 pbddr; /* Port B Data Direction Register */ - rtems_unsigned16 pbdat; /* Port B Data Register */ - rtems_unsigned16 res5; - - /* offset +82c */ - rtems_unsigned16 res6; - rtems_unsigned16 res7; - rtems_unsigned16 br0; /* Base Register (CS0) */ - rtems_unsigned16 or0; /* Option Register (CS0) */ - rtems_unsigned16 br1; /* Base Register (CS1) */ - rtems_unsigned16 or1; /* Option Register (CS1) */ - rtems_unsigned16 br2; /* Base Register (CS2) */ - rtems_unsigned16 or2; /* Option Register (CS2) */ - rtems_unsigned16 br3; /* Base Register (CS3) */ - rtems_unsigned16 or3; /* Option Register (CS3) */ - - /* offset +840 */ - rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ - rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ - rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ - rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ - rtems_unsigned8 res8; - rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ - rtems_unsigned16 wrr; /* Watchdog Reference Register */ - rtems_unsigned16 wcn; /* Watchdog Counter */ - rtems_unsigned16 res9; - rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ - rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ - rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ - rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ - rtems_unsigned8 resa; - rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ - rtems_unsigned16 resb; - rtems_unsigned16 resc; - rtems_unsigned16 resd; - - /* offset +860 */ - rtems_unsigned8 cr; /* Command Register */ - rtems_unsigned8 rese[0x1f]; - - /* offset +880, +890, +8a0 */ - m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ - - /* offset +8b0 */ - rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ - rtems_unsigned16 simask; /* Serial Interface Mask Register */ - rtems_unsigned16 simode; /* Serial Interface Mode Register */ -} m302_internalReg_t ; - - -/* - * MC68302 dual-port RAM structure. - * (Includes System RAM, Parameter RAM, and Internal Registers). - * Section 2.8 - */ -typedef struct { - rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ - rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ - m302_SCC_t scc1; /* +400 SCC1 */ - m302_SCC_t scc2; /* +500 SCC2 */ - m302_SCC_t scc3; /* +600 SCC3 */ - rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ - m302_internalReg_t reg; /* +800 68302 Internal Registers */ -} m302_dualPortRAM_t; - - -/* - * Declare the variable that's used to reference the variables in - * the dual-port RAM. - */ -extern volatile m302_dualPortRAM_t m302; - -#endif -/* end of include file */ diff --git a/cpukit/score/cpu/m68k/qsm.h b/cpukit/score/cpu/m68k/qsm.h deleted file mode 100644 index e1bf33bc12..0000000000 --- a/cpukit/score/cpu/m68k/qsm.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * QSM -- Queued Serial Module - * - * The QSM contains two serial interfaces: (a) the queued serial - * peripheral interface (QSPI) and the serial communication interface - * (SCI). The QSPI provides peripheral expansion and/or interprocessor - * communication through a full-duplex, synchronous, three-wire bus. A - * self contained RAM queue permits serial data transfers without CPU - * intervention and automatic continuous sampling. The SCI provides a - * standard non-return to zero mark/space format with wakeup functions - * to allow the CPU to run uninterrupted until woken - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family Queued Serial Module Reference Manual" (Motorola document - * QSMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _QSM_H_ -#define _QSM_H_ - - -#include <efi332.h> - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - -/* QSM_CRB (QSM Control Register Block) base address of the QSM - control registers */ -#if SIM_MM == 0 -#define QSM_CRB 0x7ffc00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define QSM_CRB 0xfffc00 -#endif - - -#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) - /* QSM Configuration Register */ -#define STOP 0x8000 /* Stop Enable */ -#define FRZ 0x6000 /* Freeze Control */ -#define SUPV 0x0080 /* Supervisor/Unrestricted */ -#define IARB 0x000f /* Inerrupt Arbitration */ - - -#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) - /* QSM Test Register */ -/* Used only for factor testing */ - - -#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) - /* QSM Interrupt Level Register */ -#define ILQSPI 0x38 /* Interrupt Level for QSPI */ -#define ILSCI 0x07 /* Interrupt Level for SCI */ - - -#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) - /* QSM Interrupt Vector Register */ -#define INTV 0xff /* Interrupt Vector Number */ - - -#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) - /* SCI Control Register 0 */ -#define SCBR 0x1fff /* SCI Baud Rate */ - - -#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) - /* SCI Control Register 1 */ -#define LOOPS 0x4000 /* Loop Mode */ -#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ -#define ILT 0x1000 /* Idle-Line Detect Type */ -#define PT 0x0800 /* Parity Type */ -#define PE 0x0400 /* Parity Enable */ -#define M 0x0200 /* Mode Select */ -#define WAKE 0x0100 /* Wakeup by Address Mark */ -#define TIE 0x0080 /* Transmit Complete Interrupt Enable */ -#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ -#define RIE 0x0020 /* Receiver Interrupt Enable */ -#define ILIE 0x0010 /* Idle-Line Interrupt Enable */ -#define TE 0x0008 /* Transmitter Enable */ -#define RE 0x0004 /* Receiver Enable */ -#define RWU 0x0002 /* Receiver Wakeup */ -#define SBK 0x0001 /* Send Break */ - - -#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) - /* SCI Status Register */ -#define TDRE 0x0100 /* Transmit Data Register Empty */ -#define TC 0x0080 /* Transmit Complete */ -#define RDRF 0x0040 /* Receive Data Register Full */ -#define RAF 0x0020 /* Receiver Active */ -#define IDLE 0x0010 /* Idle-Line Detected */ -#define OR 0x0008 /* Overrun Error */ -#define NF 0x0004 /* Noise Error Flag */ -#define FE 0x0002 /* Framing Error */ -#define PF 0x0001 /* Parity Error */ - - -#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) - /* SCI Data Register */ - - -#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) - /* Port QS Data Register */ - -#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) - /* PORT QS Pin Assignment Rgister */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a QSPI - signal. */ -/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which - case it becomes the SPI serial clock SCK. */ -/* note: PQS7 is a digital I/O pin unless the SCI transmitter is - enabled in which case it becomes the SCI serial output TxD. */ -#define QSMFun 0x0 -#define QSMDis 0x1 -/* - * PQSPAR Field | QSM Function | Discrete I/O pin - *------------------+--------------+------------------ */ -#define PQSPA0 0 /* MISO | PQS0 */ -#define PQSPA1 1 /* MOSI | PQS1 */ -#define PQSPA2 2 /* SCK | PQS2 (see note)*/ -#define PQSPA3 3 /* PCSO/!SS | PQS3 */ -#define PQSPA4 4 /* PCS1 | PQS4 */ -#define PQSPA5 5 /* PCS2 | PQS5 */ -#define PQSPA6 6 /* PCS3 | PQS6 */ -#define PQSPA7 7 /* TxD | PQS7 (see note)*/ - - -#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) - /* PORT QS Data Direction Register */ -/* Clearing a bit makes the corresponding pin an input; setting a bit - makes the pin an output. */ - - -#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) - /* QSPI Control Register 0 */ -#define MSTR 0x8000 /* Master/Slave Mode Select */ -#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ -#define BITS 0x3c00 /* Bits Per Transfer */ -#define CPOL 0x0200 /* Clock Polarity */ -#define CPHA 0x0100 /* Clock Phase */ -#define SPBR 0x00ff /* Serial Clock Baud Rate */ - - -#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) - /* QSPI Control Register 1 */ -#define SPE 0x8000 /* QSPI Enable */ -#define DSCKL 0x7f00 /* Delay before SCK */ -#define DTL 0x00ff /* Length of Delay after Transfer */ - - -#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) - /* QSPI Control Register 2 */ -#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ -#define WREN 0x4000 /* Wrap Enable */ -#define WRTO 0x2000 /* Wrap To */ -#define ENDQP 0x0f00 /* Ending Queue Pointer */ -#define NEWQP 0x000f /* New Queue Pointer Value */ - - -#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) - /* QSPI Control Register 3 */ -#define LOOPQ 0x0400 /* QSPI Loop Mode */ -#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ -#define HALT 0x0100 /* Halt */ - - -#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) - /* QSPI Status Register */ -#define SPIF 0x0080 /* QSPI Finished Flag */ -#define MODF 0x0040 /* Mode Fault Flag */ -#define HALTA 0x0020 /* Halt Acknowlwdge Flag */ -#define CPTQP x0000f /* Completed Queue Pointer */ - -#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) - /* QSPI Receive Data RAM */ -#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) - /* QSPI Transmit Data RAM */ -#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) - /* QSPI Command RAM */ - -#endif /* _QSM_H_ */ diff --git a/cpukit/score/cpu/m68k/rtems/asm.h b/cpukit/score/cpu/m68k/rtems/asm.h deleted file mode 100644 index 4ce90c1b58..0000000000 --- a/cpukit/score/cpu/m68k/rtems/asm.h +++ /dev/null @@ -1,127 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 1994. - * On-Line Applications Research Corporation (OAR). - * - * $Id$ - */ - -#ifndef __M68k_ASM_h -#define __M68k_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#define ASM -#include <rtems/score/m68k.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -#define d0 REG (d0) -#define d1 REG (d1) -#define d2 REG (d2) -#define d3 REG (d3) -#define d4 REG (d4) -#define d5 REG (d5) -#define d6 REG (d6) -#define d7 REG (d7) -#define a0 REG (a0) -#define a1 REG (a1) -#define a2 REG (a2) -#define a3 REG (a3) -#define a4 REG (a4) -#define a5 REG (a5) -#define a6 REG (a6) -#define a7 REG (a7) - -#define msp REG (msp) -#define usp REG (usp) -#define isp REG (isp) -#define sr REG (sr) - -#define fp0 REG (fp0) -#define fp1 REG (fp1) -#define fp2 REG (fp2) -#define fp3 REG (fp3) -#define fp4 REG (fp4) -#define fp5 REG (fp5) -#define fp6 REG (fp6) -#define fp7 REG (fp7) - -#define fpc REG (fpc) -#define fpi REG (fpi) -#define fps REG (fps) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h deleted file mode 100644 index da96478cf3..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h +++ /dev/null @@ -1,608 +0,0 @@ -/* - *------------------------------------------------------------------ - * - * m68302.h - Definitions for Motorola MC68302 processor. - * - * Section references in this file refer to revision 2 of Motorola's - * "MC68302 Integrated Multiprotocol Processor User's Manual". - * (Motorola document MC68302UM/AD REV 2.) - * - * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k - * on 17 February, 1993. - * - * Copyright 1995 David W. Glessner. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above copyright notice, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - * - * $Id$ - * - *------------------------------------------------------------------ - */ - -#ifndef __MOTOROLA_MC68302_DEFINITIONS_h -#define __MOTOROLA_MC68302_DEFINITIONS_h - -/* - * BAR - Base Address Register - * Section 2.7 - */ -#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) - -/* - * SCR - System Control Register - * Section 3.8.1 - */ -#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) -/* - * SCR bits - */ -#define RBIT_SCR_IPA 0x08000000 -#define RBIT_SCR_HWT 0x04000000 -#define RBIT_SCR_WPV 0x02000000 -#define RBIT_SCR_ADC 0x01000000 - -#define RBIT_SCR_ERRE 0x00400000 -#define RBIT_SCR_VGE 0x00200000 -#define RBIT_SCR_WPVE 0x00100000 -#define RBIT_SCR_RMCST 0x00080000 -#define RBIT_SCR_EMWS 0x00040000 -#define RBIT_SCR_ADCE 0x00020000 -#define RBIT_SCR_BCLM 0x00010000 - -#define RBIT_SCR_FRZW 0x00008000 -#define RBIT_SCR_FRZ2 0x00004000 -#define RBIT_SCR_FRZ1 0x00002000 -#define RBIT_SCR_SAM 0x00001000 -#define RBIT_SCR_HWDEN 0x00000800 -#define RBIT_SCR_HWDCN2 0x00000400 -#define RBIT_SCR_HWDCN1 0x00000200 -#define RBIT_SCR_HWDCN0 0x00000100 - -#define RBIT_SCR_LPREC 0x00000080 -#define RBIT_SCR_LPP16 0x00000040 -#define RBIT_SCR_LPEN 0x00000020 -#define RBIT_SCR_LPCLKDIV 0x0000001f - - -/* - * 68000 interrupt and trap vector numbers - */ -#define M68K_IVEC_BUS_ERROR 2 -#define M68K_IVEC_ADDRESS_ERROR 3 -#define M68K_IVEC_ILLEGAL_OPCODE 4 -#define M68K_IVEC_ZERO_DIVIDE 5 -#define M68K_IVEC_CHK 6 -#define M68K_IVEC_TRAPV 7 -#define M68K_IVEC_PRIVILEGE 8 -#define M68K_IVEC_TRACE 9 -#define M68K_IVEC_LINE_A 10 -#define M68K_IVEC_LINE_F 11 -/* Unassigned, Reserved 12-14 */ -#define M68K_IVEC_UNINITIALIZED_INT 15 -/* Unassigned, Reserved 16-23 */ -#define M68K_IVEC_SPURIOUS_INT 24 - -#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 -#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 -#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 -#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 -#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 -#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 -#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 - -#define M68K_IVEC_TRAP0 32 -#define M68K_IVEC_TRAP1 33 -#define M68K_IVEC_TRAP2 34 -#define M68K_IVEC_TRAP3 35 -#define M68K_IVEC_TRAP4 36 -#define M68K_IVEC_TRAP5 37 -#define M68K_IVEC_TRAP6 38 -#define M68K_IVEC_TRAP7 39 -#define M68K_IVEC_TRAP8 40 -#define M68K_IVEC_TRAP9 41 -#define M68K_IVEC_TRAP10 42 -#define M68K_IVEC_TRAP11 43 -#define M68K_IVEC_TRAP12 44 -#define M68K_IVEC_TRAP13 45 -#define M68K_IVEC_TRAP14 46 -#define M68K_IVEC_TRAP15 47 -/* - * Unassigned, Reserved 48-59 - * - * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). - */ - -/* - * MC68302 Interrupt Vectors - * Section 3.2 - */ -enum m68302_ivec_e { - M302_IVEC_ERR =0, - M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ - M302_IVEC_SMC2 =2, - M302_IVEC_SMC1 =3, - M302_IVEC_TIMER3 =4, - M302_IVEC_SCP =5, - M302_IVEC_TIMER2 =6, - M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ - M302_IVEC_SCC3 =8, - M302_IVEC_TIMER1 =9, - M302_IVEC_SCC2 =10, - M302_IVEC_IDMA =11, - M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ - M302_IVEC_SCC1 =13, - M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ - M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ - M302_IVEC_IRQ1 =17, /* External Device */ - M302_IVEC_IRQ6 =22, /* External Device */ - M302_IVEC_IRQ7 =23 /* External Device */ -}; - - -/* - * GIMR - Global Interrupt Mode Register - * Section 3.2.5.1 - */ -#define RBIT_GIMR_MOD (1<<15) -#define RBIT_GIMR_IV7 (1<<14) -#define RBIT_GIMR_IV6 (1<<13) -#define RBIT_GIMR_IV1 (1<<12) -#define RBIT_GIMR_ET7 (1<<10) -#define RBIT_GIMR_ET6 (1<<9) -#define RBIT_GIMR_ET1 (1<<8) -#define RBIT_GIMR_VECTOR (7<<5) - -/* - * IPR - Interrupt Pending Register (Section 3.2.5.2) - * IMR - Interrupt Mask Register (Section 3.2.5.3) - * ISR - Interrupt In-Service Register (Section 3.2.5.4) - */ -#define RBIT_IPR_PB11 (1<<15) -#define RBIT_IPR_PB10 (1<<14) -#define RBIT_IPR_SCC1 (1<<13) -#define RBIT_IPR_SDMA (1<<12) -#define RBIT_IPR_IDMA (1<<11) -#define RBIT_IPR_SCC2 (1<<10) -#define RBIT_IPR_TIMER1 (1<<9) -#define RBIT_IPR_SCC3 (1<<8) -#define RBIT_IPR_PB9 (1<<7) -#define RBIT_IPR_TIMER2 (1<<6) -#define RBIT_IPR_SCP (1<<5) -#define RBIT_IPR_TIMER3 (1<<4) -#define RBIT_IPR_SMC1 (1<<3) -#define RBIT_IPR_SMC2 (1<<2) -#define RBIT_IPR_PB8 (1<<1) -#define RBIT_IPR_ERR (1<<0) - -#define RBIT_ISR_PB11 (1<<15) -#define RBIT_ISR_PB10 (1<<14) -#define RBIT_ISR_SCC1 (1<<13) -#define RBIT_ISR_SDMA (1<<12) -#define RBIT_ISR_IDMA (1<<11) -#define RBIT_ISR_SCC2 (1<<10) -#define RBIT_ISR_TIMER1 (1<<9) -#define RBIT_ISR_SCC3 (1<<8) -#define RBIT_ISR_PB9 (1<<7) -#define RBIT_ISR_TIMER2 (1<<6) -#define RBIT_ISR_SCP (1<<5) -#define RBIT_ISR_TIMER3 (1<<4) -#define RBIT_ISR_SMC1 (1<<3) -#define RBIT_ISR_SMC2 (1<<2) -#define RBIT_ISR_PB8 (1<<1) - -#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ -#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ -#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ -#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ -#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ -#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ -#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ -#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ -#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ -#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ -#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ -#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ -#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ -#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ -#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ - - -/* - * DRAM Refresh - * Section 3.9 - * - * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 - * structures in the parameter RAM. - * - * Access to the DRAM registers can be accomplished by - * the following approach: - * - * volatile m302_DRAM_refresh_t *dram; - * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; - * - * Then simply use pointer references (e.g. dram->count = 3). - */ -typedef struct { - rtems_unsigned16 dram_high; /* DRAM high address and FC */ - rtems_unsigned16 dram_low; /* DRAM low address */ - rtems_unsigned16 increment; /* increment step (bytes/row) */ - rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ - rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ - rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ - rtems_unsigned16 t_count; /* temporary refresh cycles count */ - rtems_unsigned16 res; /* reserved */ -} m302_DRAM_refresh_t; - - -/* - * TMR - Timer Mode Register (for timers 1 and 2) - * Section 3.5.2.1 - */ -#define RBIT_TMR_ICLK_STOP (0<<1) -#define RBIT_TMR_ICLK_MASTER (1<<1) -#define RBIT_TMR_ICLK_MASTER16 (2<<1) -#define RBIT_TMR_ICLK_TIN (3<<1) - -#define RBIT_TMR_OM (1<<5) -#define RBIT_TMR_ORI (1<<4) -#define RBIT_TMR_FRR (1<<3) -#define RBIT_TMR_RST (1<<0) - - -/* - * TER - Timer Event Register (for timers 1 and 2) - * Section 3.5.2.5 - */ -#define RBIT_TER_REF (1<<1) /* Output Reference Event */ -#define RBIT_TER_CAP (1<<0) /* Capture Event */ - - -/* - * SCC Buffer Descriptors and Buffer Descriptors Table - * Section 4.5.5 - */ -typedef struct m302_SCC_bd { - rtems_unsigned16 status; /* status and control */ - rtems_unsigned16 length; /* data length */ - rtems_unsigned8 *buffer; /* data buffer pointer */ -} m302_SCC_bd_t; - -typedef struct { - m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ - m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ -} m302_SCC_bd_table_t; - - -/* - * SCC Parameter RAM (offset 0x080 from an SCC Base) - * Section 4.5.6 - * - * Each SCC parameter RAM area begins at offset 0x80 from each SCC base - * area (0x400, 0x500, or 0x600 from the dual-port RAM base). - * - * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific - * portion of the SCC parameter RAM. - */ -typedef struct { - rtems_unsigned8 rfcr; /* Rx Function Code */ - rtems_unsigned8 tfcr; /* Tx Function Code */ - rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ - rtems_unsigned16 _rstate; /* Rx Internal State */ - rtems_unsigned8 res2; - rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ - rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ - rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ - rtems_unsigned16 _rtmp; /* Rx Temp */ - rtems_unsigned16 _tstate; /* Tx Internal State */ - rtems_unsigned8 res7; - rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ - rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ - rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ - rtems_unsigned16 _ttmp; /* Tx Temp */ -} m302_SCC_parameters_t; - -/* - * UART-Specific SCC Parameter RAM - * Section 4.5.11.3 - */ -typedef struct { - rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ - rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ - rtems_unsigned16 brkcr; /* Break Count Register (tx) */ - rtems_unsigned16 parec; /* Receive Parity Error Counter */ - rtems_unsigned16 frmec; /* Receive Framing Error Counter */ - rtems_unsigned16 nosec; /* Receive Noise Counter */ - rtems_unsigned16 brkec; /* Receive Break Condition Counter */ - rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ - rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ - rtems_unsigned16 rccr; /* Receive Control Character Register */ - rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ -} m302_SCC_UartSpecific_t; -/* - * This definition allows for the checking of receive buffers - * for errors. - */ - -#define RCV_ERR 0x003F - -/* - * UART receive buffer descriptor bit definitions. - * Section 4.5.11.14 - */ -#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ -#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ -#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ -#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ -#define RBIT_UART_BR (1<<5) /* break sequence was received */ -#define RBIT_UART_FR (1<<4) /* framing error was received */ -#define RBIT_UART_PR (1<<3) /* parity error was received */ -#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ -#define RBIT_UART_CD (1<<0) /* carrier detect lost */ -#define RBIT_UART_STATUS 0x003B /* all status bits */ - -/* - * UART transmit buffer descriptor bit definitions. - * Section 4.5.11.15 - */ -#define RBIT_UART_CR (1<<11) /* clear-to-send report - * this results in two idle bits - * between back-to-back frames - */ -#define RBIT_UART_A (1<<10) /* buffer contains address characters - * only valid in multidrop mode (UM0=1) - */ -#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ -#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ - -/* - * UART event register - * Section 4.5.11.16 - */ -#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ -#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ -#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ -#define M302_UART_EV_BRK (1<<4) /* break character was received */ -#define M302_UART_EV_CCR (1<<3) /* control character received */ -#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ -#define M302_UART_EV_RX (1<<0) /* buffer has been received */ - - -/* - * HDLC-Specific SCC Parameter RAM - * Section 4.5.12.3 - * - * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC - * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC - */ -typedef struct { - rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ - rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ - rtems_unsigned16 c_mask_l; /* CRC Mask Low */ - rtems_unsigned16 c_mask_h; /* CRC Mask High */ - rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ - rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ - - rtems_unsigned16 disfc; /* Discard Frame Counter */ - rtems_unsigned16 crcec; /* CRC Error Counter */ - rtems_unsigned16 abtsc; /* Abort Sequence Counter */ - rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ - rtems_unsigned16 retrc; /* Frame Retransmission Counter */ - - rtems_unsigned16 mflr; /* Maximum Frame Length Register */ - rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ - - rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ - rtems_unsigned16 haddr1; /* User Defined Frame Address */ - rtems_unsigned16 haddr2; /* " */ - rtems_unsigned16 haddr3; /* " */ - rtems_unsigned16 haddr4; /* " */ -} m302_SCC_HdlcSpecific_t; -/* - * HDLC receiver buffer descriptor bit definitions - * Section 4.5.12.10 - */ -#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ -#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ -#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ -#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ -#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ -#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ -#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ -#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ - -/* - * HDLC transmit buffer descriptor bit definitions - * Section 4.5.12.11 - */ -#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ -#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ -#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ -#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ -#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ -#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ -#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ -#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ - -/* - * HDLC event register bit definitions - * Section 4.5.12.12 - */ -#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ -#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ -#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ -#define RBIT_HDLC_TXE 0x10 /* transmit error */ -#define RBIT_HDLC_RXF 0x08 /* received frame */ -#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to - * lack of buffers - */ -#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ -#define RBIT_HDLC_RXB 0x01 /* received buffer */ - - - -typedef struct { - m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ - m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ - union { /* +09C Protocol-Specific Parm RAM */ - m302_SCC_UartSpecific_t uart; - m302_SCC_HdlcSpecific_t hdlc; - } prot; - rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ -} m302_SCC_t; - - -/* - * Common SCC Registers - */ -typedef struct { - rtems_unsigned16 res1; - rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ - rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ - rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ - rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ - rtems_unsigned8 res2; - rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ - rtems_unsigned8 res3; - rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ - rtems_unsigned8 res4; - rtems_unsigned16 res5; -} m302_SCC_Registers_t; - -/* - * SCON - SCC Configuration Register - * Section 4.5.2 - */ -#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) - * When set, the TXD driver is an - * open-drain output */ -#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ -#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ -#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ - -/* - * SCM - SCC Mode Register bit definitions - * Section 4.5.3 - * The parameter-specific mode bits occupy bits 15 through 6. - */ -#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ -#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ - - -/* - * Internal MC68302 Registers - * starts at offset 0x800 from dual-port RAM base - * Section 2.8 - */ -typedef struct { - /* offset +800 */ - rtems_unsigned16 res0; - rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ - rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ - rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ - rtems_unsigned16 bcr; /* IDMA Byte Count Register */ - rtems_unsigned8 csr; /* IDMA Channel Status Register */ - rtems_unsigned8 res1; - rtems_unsigned8 fcr; /* IDMA Function Code Register */ - rtems_unsigned8 res2; - - /* offset +812 */ - rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ - rtems_unsigned16 ipr; /* Interrupt Pending Register */ - rtems_unsigned16 imr; /* Interrupt Mask Register */ - rtems_unsigned16 isr; /* Interrupt In-Service Register */ - rtems_unsigned16 res3; - rtems_unsigned16 res4; - - /* offset +81e */ - rtems_unsigned16 pacnt; /* Port A Control Register */ - rtems_unsigned16 paddr; /* Port A Data Direction Register */ - rtems_unsigned16 padat; /* Port A Data Register */ - rtems_unsigned16 pbcnt; /* Port B Control Register */ - rtems_unsigned16 pbddr; /* Port B Data Direction Register */ - rtems_unsigned16 pbdat; /* Port B Data Register */ - rtems_unsigned16 res5; - - /* offset +82c */ - rtems_unsigned16 res6; - rtems_unsigned16 res7; - rtems_unsigned16 br0; /* Base Register (CS0) */ - rtems_unsigned16 or0; /* Option Register (CS0) */ - rtems_unsigned16 br1; /* Base Register (CS1) */ - rtems_unsigned16 or1; /* Option Register (CS1) */ - rtems_unsigned16 br2; /* Base Register (CS2) */ - rtems_unsigned16 or2; /* Option Register (CS2) */ - rtems_unsigned16 br3; /* Base Register (CS3) */ - rtems_unsigned16 or3; /* Option Register (CS3) */ - - /* offset +840 */ - rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ - rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ - rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ - rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ - rtems_unsigned8 res8; - rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ - rtems_unsigned16 wrr; /* Watchdog Reference Register */ - rtems_unsigned16 wcn; /* Watchdog Counter */ - rtems_unsigned16 res9; - rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ - rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ - rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ - rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ - rtems_unsigned8 resa; - rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ - rtems_unsigned16 resb; - rtems_unsigned16 resc; - rtems_unsigned16 resd; - - /* offset +860 */ - rtems_unsigned8 cr; /* Command Register */ - rtems_unsigned8 rese[0x1f]; - - /* offset +880, +890, +8a0 */ - m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ - - /* offset +8b0 */ - rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ - rtems_unsigned16 simask; /* Serial Interface Mask Register */ - rtems_unsigned16 simode; /* Serial Interface Mode Register */ -} m302_internalReg_t ; - - -/* - * MC68302 dual-port RAM structure. - * (Includes System RAM, Parameter RAM, and Internal Registers). - * Section 2.8 - */ -typedef struct { - rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ - rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ - m302_SCC_t scc1; /* +400 SCC1 */ - m302_SCC_t scc2; /* +500 SCC2 */ - m302_SCC_t scc3; /* +600 SCC3 */ - rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ - m302_internalReg_t reg; /* +800 68302 Internal Registers */ -} m302_dualPortRAM_t; - - -/* - * Declare the variable that's used to reference the variables in - * the dual-port RAM. - */ -extern volatile m302_dualPortRAM_t m302; - -#endif -/* end of include file */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h deleted file mode 100644 index e1bf33bc12..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * QSM -- Queued Serial Module - * - * The QSM contains two serial interfaces: (a) the queued serial - * peripheral interface (QSPI) and the serial communication interface - * (SCI). The QSPI provides peripheral expansion and/or interprocessor - * communication through a full-duplex, synchronous, three-wire bus. A - * self contained RAM queue permits serial data transfers without CPU - * intervention and automatic continuous sampling. The SCI provides a - * standard non-return to zero mark/space format with wakeup functions - * to allow the CPU to run uninterrupted until woken - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family Queued Serial Module Reference Manual" (Motorola document - * QSMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _QSM_H_ -#define _QSM_H_ - - -#include <efi332.h> - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - -/* QSM_CRB (QSM Control Register Block) base address of the QSM - control registers */ -#if SIM_MM == 0 -#define QSM_CRB 0x7ffc00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define QSM_CRB 0xfffc00 -#endif - - -#define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) - /* QSM Configuration Register */ -#define STOP 0x8000 /* Stop Enable */ -#define FRZ 0x6000 /* Freeze Control */ -#define SUPV 0x0080 /* Supervisor/Unrestricted */ -#define IARB 0x000f /* Inerrupt Arbitration */ - - -#define QTEST (volatile unsigned short int * const)(0x02 + QSM_CRB) - /* QSM Test Register */ -/* Used only for factor testing */ - - -#define QILR (volatile unsigned char * const)(0x04 + QSM_CRB) - /* QSM Interrupt Level Register */ -#define ILQSPI 0x38 /* Interrupt Level for QSPI */ -#define ILSCI 0x07 /* Interrupt Level for SCI */ - - -#define QIVR (volatile unsigned char * const)(0x05 + QSM_CRB) - /* QSM Interrupt Vector Register */ -#define INTV 0xff /* Interrupt Vector Number */ - - -#define SCCR0 (volatile unsigned short int * const)(0x08 + QSM_CRB) - /* SCI Control Register 0 */ -#define SCBR 0x1fff /* SCI Baud Rate */ - - -#define SCCR1 (volatile unsigned short int * const)(0x0a + QSM_CRB) - /* SCI Control Register 1 */ -#define LOOPS 0x4000 /* Loop Mode */ -#define WOMS 0x2000 /* Wired-OR Mode for SCI Pins */ -#define ILT 0x1000 /* Idle-Line Detect Type */ -#define PT 0x0800 /* Parity Type */ -#define PE 0x0400 /* Parity Enable */ -#define M 0x0200 /* Mode Select */ -#define WAKE 0x0100 /* Wakeup by Address Mark */ -#define TIE 0x0080 /* Transmit Complete Interrupt Enable */ -#define TCIE 0x0040 /* Transmit Complete Interrupt Enable */ -#define RIE 0x0020 /* Receiver Interrupt Enable */ -#define ILIE 0x0010 /* Idle-Line Interrupt Enable */ -#define TE 0x0008 /* Transmitter Enable */ -#define RE 0x0004 /* Receiver Enable */ -#define RWU 0x0002 /* Receiver Wakeup */ -#define SBK 0x0001 /* Send Break */ - - -#define SCSR (volatile unsigned short int * const)(0x0c + QSM_CRB) - /* SCI Status Register */ -#define TDRE 0x0100 /* Transmit Data Register Empty */ -#define TC 0x0080 /* Transmit Complete */ -#define RDRF 0x0040 /* Receive Data Register Full */ -#define RAF 0x0020 /* Receiver Active */ -#define IDLE 0x0010 /* Idle-Line Detected */ -#define OR 0x0008 /* Overrun Error */ -#define NF 0x0004 /* Noise Error Flag */ -#define FE 0x0002 /* Framing Error */ -#define PF 0x0001 /* Parity Error */ - - -#define SCDR (volatile unsigned short int * const)(0x0e + QSM_CRB) - /* SCI Data Register */ - - -#define PORTQS (volatile unsigned char * const)(0x15 + QSM_CRB) - /* Port QS Data Register */ - -#define PQSPAR (volatile unsigned char * const)(0x16 + QSM_CRB) - /* PORT QS Pin Assignment Rgister */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a QSPI - signal. */ -/* note: PQS2 is a digital I/O pin unless the SPI is enabled in which - case it becomes the SPI serial clock SCK. */ -/* note: PQS7 is a digital I/O pin unless the SCI transmitter is - enabled in which case it becomes the SCI serial output TxD. */ -#define QSMFun 0x0 -#define QSMDis 0x1 -/* - * PQSPAR Field | QSM Function | Discrete I/O pin - *------------------+--------------+------------------ */ -#define PQSPA0 0 /* MISO | PQS0 */ -#define PQSPA1 1 /* MOSI | PQS1 */ -#define PQSPA2 2 /* SCK | PQS2 (see note)*/ -#define PQSPA3 3 /* PCSO/!SS | PQS3 */ -#define PQSPA4 4 /* PCS1 | PQS4 */ -#define PQSPA5 5 /* PCS2 | PQS5 */ -#define PQSPA6 6 /* PCS3 | PQS6 */ -#define PQSPA7 7 /* TxD | PQS7 (see note)*/ - - -#define DDRQS (volatile unsigned char * const)(0x17 + QSM_CRB) - /* PORT QS Data Direction Register */ -/* Clearing a bit makes the corresponding pin an input; setting a bit - makes the pin an output. */ - - -#define SPCR0 (volatile unsigned short int * const)(0x18 + QSM_CRB) - /* QSPI Control Register 0 */ -#define MSTR 0x8000 /* Master/Slave Mode Select */ -#define WOMQ 0x4000 /* Wired-OR Mode for QSPI Pins */ -#define BITS 0x3c00 /* Bits Per Transfer */ -#define CPOL 0x0200 /* Clock Polarity */ -#define CPHA 0x0100 /* Clock Phase */ -#define SPBR 0x00ff /* Serial Clock Baud Rate */ - - -#define SPCR1 (volatile unsigned short int * const)(0x1a + QSM_CRB) - /* QSPI Control Register 1 */ -#define SPE 0x8000 /* QSPI Enable */ -#define DSCKL 0x7f00 /* Delay before SCK */ -#define DTL 0x00ff /* Length of Delay after Transfer */ - - -#define SPCR2 (volatile unsigned short int * const)(0x1c + QSM_CRB) - /* QSPI Control Register 2 */ -#define SPIFIE 0x8000 /* SPI Finished Interrupt Enable */ -#define WREN 0x4000 /* Wrap Enable */ -#define WRTO 0x2000 /* Wrap To */ -#define ENDQP 0x0f00 /* Ending Queue Pointer */ -#define NEWQP 0x000f /* New Queue Pointer Value */ - - -#define SPCR3 (volatile unsigned char * const)(0x1e + QSM_CRB) - /* QSPI Control Register 3 */ -#define LOOPQ 0x0400 /* QSPI Loop Mode */ -#define HMIE 0x0200 /* HALTA and MODF Interrupt Enable */ -#define HALT 0x0100 /* Halt */ - - -#define SPSR (volatile unsigned char * const)(0x1f + QSM_CRB) - /* QSPI Status Register */ -#define SPIF 0x0080 /* QSPI Finished Flag */ -#define MODF 0x0040 /* Mode Fault Flag */ -#define HALTA 0x0020 /* Halt Acknowlwdge Flag */ -#define CPTQP x0000f /* Completed Queue Pointer */ - -#define QSPIRR (volatile unsigned char * const)(0x100 + QSM_CRB) - /* QSPI Receive Data RAM */ -#define QSPITR (volatile unsigned char * const)(0x120 + QSM_CRB) - /* QSPI Transmit Data RAM */ -#define QSPIcR (volatile unsigned char * const)(0x140 + QSM_CRB) - /* QSPI Command RAM */ - -#endif /* _QSM_H_ */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h deleted file mode 100644 index fae7fe8783..0000000000 --- a/cpukit/score/cpu/m68k/rtems/m68k/sim.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * SIM -- System Integration Module - * - * The system integration module (SIM) is used on many Motorola 16- - * and 32-bit MCUs for the following functions: - * - * () System configuration and protection. Bus and software watchdog - * monitors are provided in addition to periodic interrupt generators. - * - * () Clock signal generation for other intermodule bus (IMB) members - * and external devices. - * - * () The generation of chip-select signals that simplify external - * circuitry interface. - * - * () Data ports that are available for general purpose input and - * output. - * - * () A system test block that is intended only for factory tests. - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family System Integration Module Reference Manual" (Motorola document - * SIMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _SIM_H_ -#define _SIM_H_ - - -#include <efi332.h> - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - - -/* SIM_CRB (SIM Control Register Block) base address of the SIM - control registers */ -/* not included in ram_init.h */ -#if SIM_MM == 0 -#define SIM_CRB 0x7ffa00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define SIM_CRB 0xfffa00 -#endif -/* end not included in ram_init.h */ - - - -#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB) - /* Module Configuration Register */ -#define EXOFF 0x8000 /* External Clock Off */ -#define FRZSW 0x4000 /* Freeze Software Enable */ -#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ -#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ -#define SHEN 0x0300 /* Show Cycle Enable */ -#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ -#define MM 0x0040 /* Module Mapping */ -#define IARB 0x000f /* Interrupt Arbitration Field */ - - - -#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB) - /* SIM Test Register */ -/* Used only for factor testing */ - - - -#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB) - /* Clock Synthesizer Control Register */ -#define W 0x8000 /* Frequency Control (VCO) */ -#define X 0x4000 /* Frequency Control Bit (Prescale) */ -#define Y 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ - - - -#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB) - /* Reset Status Register */ -#define EXT 0x0080 /* External Reset */ -#define POW 0x0040 /* Power-On Reset */ -#define SW 0x0020 /* Software Watchdog Reset */ -#define DBF 0x0010 /* Double Bus Fault Reset */ -#define LOC 0x0004 /* Loss of Clock Reset */ -#define SYS 0x0002 /* System Reset */ -#define TST 0x0001 /* Test Submodule Reset */ - - - -#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB) - /* System Integration Test Register */ -/* Used only for factor testing */ - - - -#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB) -#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB) - /* Port E Data Register */ -#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB) - /* Port E Data Direction Register */ -#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB) - /* Port E Pin Assignment Register */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB) -#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB) - /* Port F Data Register */ -#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB) - /* Port E Data Direction Register */ -#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB) -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB) -/* !!! can write to only once after reset !!! */ - /* System Protection Control Register */ -#define SWE 0x80 /* Software Watch Enable */ -#define SWP 0x40 /* Software Watchdog Prescale */ -#define SWT 0x30 /* Software Watchdog Timing */ -#define HME 0x08 /* Halt Monitor Enable */ -#define BME 0x04 /* Bus Monitor External Enable */ -#define BMT 0x03 /* Bus Monitor Timing */ - - - -#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB) - /* Periodic Interrupt Control Reg. */ -#define PIRQL 0x0700 /* Periodic Interrupt Request Level */ -#define PIV 0x00ff /* Periodic Interrupt Level */ - - - -#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB) - /* Periodic Interrupt Timer Register */ -#define PTP 0x0100 /* Periodic Timer Prescaler Control */ -#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ - - - -#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB) - /* Software Service Register */ -/* write 0x55 then 0xaa to service the software watchdog */ - - - -#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB) - /* Test Module Shift Count */ -#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB) - /* Test Module Repetition Counter */ -#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB) - /* Test Module Control */ -#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB) - /* Test Module Distributed */ -/* Used only for factor testing */ - - - -#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB) - /* Port C Data */ - - - -#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB) - /* Chip Select Pin Assignment - Resgister 0 */ -/* CSPAR0 contains seven two-bit fields that determine the functions - of corresponding chip-select pins. CSPAR0[15:14] are not - used. These bits always read zero; write have no effect. CSPAR0 bit - 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ -#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB) - /* Chip Select Pin Assignment - Register 1 */ -/* CSPAR1 contains five two-bit fields that determine the finctions of - corresponding chip-select pins. CSPAR1[15:10] are not used. These - bits always read zero; writes have no effect. */ -/* - * - * Bit Field | Description - * ------------+--------------- - * 00 | Discrete Output - * 01 | Alternate Function - * 10 | Chip Select (8-bit port) - * 11 | Chip Select (16-bit port) - */ -#define DisOut 0x0 -#define AltFun 0x1 -#define CS8bit 0x2 -#define CS16bit 0x3 -/* - * - * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output - *-----------------+--------------------+--------------------+---------------*/ -#define CS_5 12 /* !CS5 | FC2 | PC2 */ -#define CS_4 10 /* !CS4 | FC1 | PC1 */ -#define CS_3 8 /* !CS3 | FC0 | PC0 */ -#define CS_2 6 /* !CS2 | !BGACK | */ -#define CS_1 4 /* !CS1 | !BG | */ -#define CS_0 2 /* !CS0 | !BR | */ -#define CSBOOT 0 /* !CSBOOT | | */ -/* | | | */ -#define CS_10 8 /* !CS10 | ADDR23 | ECLK */ -#define CS_9 6 /* !CS9 | ADDR22 | PC6 */ -#define CS_8 4 /* !CS8 | ADDR21 | PC5 */ -#define CS_7 2 /* !CS7 | ADDR20 | PC4 */ -#define CS_6 0 /* !CS6 | ADDR19 | PC3 */ - -#define BS_2K 0x0 -#define BS_8K 0x1 -#define BS_16K 0x2 -#define BS_64K 0x3 -#define BS_128K 0x4 -#define BS_256K 0x5 -#define BS_512K 0x6 -#define BS_1M 0x7 - -#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB) -#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB) -#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB) -#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB) -#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB) -#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB) -#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB) -#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB) -#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB) -#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB) -#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB) -#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB) - -#define MODE 0x8000 -#define Disable 0 -#define LowerByte 0x2000 -#define UpperByte 0x4000 -#define BothBytes 0x6000 -#define ReadOnly 0x0800 -#define WriteOnly 0x1000 -#define ReadWrite 0x1800 -#define SyncAS 0x0 -#define SyncDS 0x0400 - -#define WaitStates_0 (0x0 << 6) -#define WaitStates_1 (0x1 << 6) -#define WaitStates_2 (0x2 << 6) -#define WaitStates_3 (0x3 << 6) -#define WaitStates_4 (0x4 << 6) -#define WaitStates_5 (0x5 << 6) -#define WaitStates_6 (0x6 << 6) -#define WaitStates_7 (0x7 << 6) -#define WaitStates_8 (0x8 << 6) -#define WaitStates_9 (0x9 << 6) -#define WaitStates_10 (0xa << 6) -#define WaitStates_11 (0xb << 6) -#define WaitStates_12 (0xc << 6) -#define WaitStates_13 (0xd << 6) -#define FastTerm (0xe << 6) -#define External (0xf << 6) - -#define CPUSpace (0x0 << 4) -#define UserSpace (0x1 << 4) -#define SupSpace (0x2 << 4) -#define UserSupSpace (0x3 << 4) - -#define IPLevel_any 0x0 -#define IPLevel_1 0x2 -#define IPLevel_2 0x4 -#define IPLevel_3 0x6 -#define IPLevel_4 0x8 -#define IPLevel_5 0xa -#define IPLevel_6 0xc -#define IPLevel_7 0xe - -#define AVEC 1 - -#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB) -#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB) -#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB) -#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB) -#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB) -#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB) -#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB) -#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB) -#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB) -#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB) -#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB) -#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB) - -#endif /* _SIM_h_ */ diff --git a/cpukit/score/cpu/m68k/sim.h b/cpukit/score/cpu/m68k/sim.h deleted file mode 100644 index fae7fe8783..0000000000 --- a/cpukit/score/cpu/m68k/sim.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - *------------------------------------------------------------------- - * - * SIM -- System Integration Module - * - * The system integration module (SIM) is used on many Motorola 16- - * and 32-bit MCUs for the following functions: - * - * () System configuration and protection. Bus and software watchdog - * monitors are provided in addition to periodic interrupt generators. - * - * () Clock signal generation for other intermodule bus (IMB) members - * and external devices. - * - * () The generation of chip-select signals that simplify external - * circuitry interface. - * - * () Data ports that are available for general purpose input and - * output. - * - * () A system test block that is intended only for factory tests. - * - * For more information, refer to Motorola's "Modular Microcontroller - * Family System Integration Module Reference Manual" (Motorola document - * SIMRM/AD). - * - * This file has been created by John S. Gwynne for support of - * Motorola's 68332 MCU in the efi332 project. - * - * Redistribution and use in source and binary forms are permitted - * provided that the following conditions are met: - * 1. Redistribution of source code and documentation must retain - * the above authorship, this list of conditions and the - * following disclaimer. - * 2. The name of the author may not be used to endorse or promote - * products derived from this software without specific prior - * written permission. - * - * This software is provided "AS IS" without warranty of any kind, - * either expressed or implied, including, but not limited to, the - * implied warranties of merchantability, title and fitness for a - * particular purpose. - * - *------------------------------------------------------------------ - * - * $Id$ - */ - -#ifndef _SIM_H_ -#define _SIM_H_ - - -#include <efi332.h> - - -/* SAM-- shift and mask */ -#undef SAM -#define SAM(a,b,c) ((a << b) & c) - - - -/* SIM_CRB (SIM Control Register Block) base address of the SIM - control registers */ -/* not included in ram_init.h */ -#if SIM_MM == 0 -#define SIM_CRB 0x7ffa00 -#else -#undef SIM_MM -#define SIM_MM 1 -#define SIM_CRB 0xfffa00 -#endif -/* end not included in ram_init.h */ - - - -#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB) - /* Module Configuration Register */ -#define EXOFF 0x8000 /* External Clock Off */ -#define FRZSW 0x4000 /* Freeze Software Enable */ -#define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ -#define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ -#define SHEN 0x0300 /* Show Cycle Enable */ -#define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ -#define MM 0x0040 /* Module Mapping */ -#define IARB 0x000f /* Interrupt Arbitration Field */ - - - -#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB) - /* SIM Test Register */ -/* Used only for factor testing */ - - - -#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB) - /* Clock Synthesizer Control Register */ -#define W 0x8000 /* Frequency Control (VCO) */ -#define X 0x4000 /* Frequency Control Bit (Prescale) */ -#define Y 0x3f00 /* Frequency Control Counter */ -#define EDIV 0x0080 /* ECLK Divide Rate */ -#define SLIMP 0x0010 /* Limp Mode Status */ -#define SLOCK 0x0008 /* Synthesizer Lock */ -#define RSTEN 0x0004 /* Reset Enable */ -#define STSIM 0x0002 /* Stop Mode SIM Clock */ -#define STEXT 0x0001 /* Stop Mode External Clock */ - - - -#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB) - /* Reset Status Register */ -#define EXT 0x0080 /* External Reset */ -#define POW 0x0040 /* Power-On Reset */ -#define SW 0x0020 /* Software Watchdog Reset */ -#define DBF 0x0010 /* Double Bus Fault Reset */ -#define LOC 0x0004 /* Loss of Clock Reset */ -#define SYS 0x0002 /* System Reset */ -#define TST 0x0001 /* Test Submodule Reset */ - - - -#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB) - /* System Integration Test Register */ -/* Used only for factor testing */ - - - -#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB) -#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB) - /* Port E Data Register */ -#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB) - /* Port E Data Direction Register */ -#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB) - /* Port E Pin Assignment Register */ -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB) -#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB) - /* Port F Data Register */ -#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB) - /* Port E Data Direction Register */ -#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB) -/* Any bit cleared (zero) defines the corresponding pin to be an I/O - pin. Any bit set defines the corresponding pin to be a bus control - signal. */ - - - -#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB) -/* !!! can write to only once after reset !!! */ - /* System Protection Control Register */ -#define SWE 0x80 /* Software Watch Enable */ -#define SWP 0x40 /* Software Watchdog Prescale */ -#define SWT 0x30 /* Software Watchdog Timing */ -#define HME 0x08 /* Halt Monitor Enable */ -#define BME 0x04 /* Bus Monitor External Enable */ -#define BMT 0x03 /* Bus Monitor Timing */ - - - -#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB) - /* Periodic Interrupt Control Reg. */ -#define PIRQL 0x0700 /* Periodic Interrupt Request Level */ -#define PIV 0x00ff /* Periodic Interrupt Level */ - - - -#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB) - /* Periodic Interrupt Timer Register */ -#define PTP 0x0100 /* Periodic Timer Prescaler Control */ -#define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ - - - -#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB) - /* Software Service Register */ -/* write 0x55 then 0xaa to service the software watchdog */ - - - -#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB) - /* Test Module Master Shift A */ -#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB) - /* Test Module Shift Count */ -#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB) - /* Test Module Repetition Counter */ -#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB) - /* Test Module Control */ -#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB) - /* Test Module Distributed */ -/* Used only for factor testing */ - - - -#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB) - /* Port C Data */ - - - -#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB) - /* Chip Select Pin Assignment - Resgister 0 */ -/* CSPAR0 contains seven two-bit fields that determine the functions - of corresponding chip-select pins. CSPAR0[15:14] are not - used. These bits always read zero; write have no effect. CSPAR0 bit - 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ -#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB) - /* Chip Select Pin Assignment - Register 1 */ -/* CSPAR1 contains five two-bit fields that determine the finctions of - corresponding chip-select pins. CSPAR1[15:10] are not used. These - bits always read zero; writes have no effect. */ -/* - * - * Bit Field | Description - * ------------+--------------- - * 00 | Discrete Output - * 01 | Alternate Function - * 10 | Chip Select (8-bit port) - * 11 | Chip Select (16-bit port) - */ -#define DisOut 0x0 -#define AltFun 0x1 -#define CS8bit 0x2 -#define CS16bit 0x3 -/* - * - * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output - *-----------------+--------------------+--------------------+---------------*/ -#define CS_5 12 /* !CS5 | FC2 | PC2 */ -#define CS_4 10 /* !CS4 | FC1 | PC1 */ -#define CS_3 8 /* !CS3 | FC0 | PC0 */ -#define CS_2 6 /* !CS2 | !BGACK | */ -#define CS_1 4 /* !CS1 | !BG | */ -#define CS_0 2 /* !CS0 | !BR | */ -#define CSBOOT 0 /* !CSBOOT | | */ -/* | | | */ -#define CS_10 8 /* !CS10 | ADDR23 | ECLK */ -#define CS_9 6 /* !CS9 | ADDR22 | PC6 */ -#define CS_8 4 /* !CS8 | ADDR21 | PC5 */ -#define CS_7 2 /* !CS7 | ADDR20 | PC4 */ -#define CS_6 0 /* !CS6 | ADDR19 | PC3 */ - -#define BS_2K 0x0 -#define BS_8K 0x1 -#define BS_16K 0x2 -#define BS_64K 0x3 -#define BS_128K 0x4 -#define BS_256K 0x5 -#define BS_512K 0x6 -#define BS_1M 0x7 - -#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB) -#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB) -#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB) -#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB) -#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB) -#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB) -#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB) -#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB) -#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB) -#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB) -#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB) -#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB) - -#define MODE 0x8000 -#define Disable 0 -#define LowerByte 0x2000 -#define UpperByte 0x4000 -#define BothBytes 0x6000 -#define ReadOnly 0x0800 -#define WriteOnly 0x1000 -#define ReadWrite 0x1800 -#define SyncAS 0x0 -#define SyncDS 0x0400 - -#define WaitStates_0 (0x0 << 6) -#define WaitStates_1 (0x1 << 6) -#define WaitStates_2 (0x2 << 6) -#define WaitStates_3 (0x3 << 6) -#define WaitStates_4 (0x4 << 6) -#define WaitStates_5 (0x5 << 6) -#define WaitStates_6 (0x6 << 6) -#define WaitStates_7 (0x7 << 6) -#define WaitStates_8 (0x8 << 6) -#define WaitStates_9 (0x9 << 6) -#define WaitStates_10 (0xa << 6) -#define WaitStates_11 (0xb << 6) -#define WaitStates_12 (0xc << 6) -#define WaitStates_13 (0xd << 6) -#define FastTerm (0xe << 6) -#define External (0xf << 6) - -#define CPUSpace (0x0 << 4) -#define UserSpace (0x1 << 4) -#define SupSpace (0x2 << 4) -#define UserSupSpace (0x3 << 4) - -#define IPLevel_any 0x0 -#define IPLevel_1 0x2 -#define IPLevel_2 0x4 -#define IPLevel_3 0x6 -#define IPLevel_4 0x8 -#define IPLevel_5 0xa -#define IPLevel_6 0xc -#define IPLevel_7 0xe - -#define AVEC 1 - -#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB) -#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB) -#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB) -#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB) -#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB) -#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB) -#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB) -#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB) -#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB) -#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB) -#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB) -#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB) - -#endif /* _SIM_h_ */ |