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| author | Eric Norum <WENorum@lbl.gov> | 2005-01-28 19:48:25 +0000 |
|---|---|---|
| committer | Eric Norum <WENorum@lbl.gov> | 2005-01-28 19:48:25 +0000 |
| commit | fa9fa1e42233f5ee7da7d4a2b4ed0c5d848926f4 (patch) | |
| tree | f63b5a273a2857c88c6fddb96e4a623295d0fc29 /cpukit/score/cpu/m68k/rtems/score | |
| parent | New BSP/CPU. (diff) | |
| download | rtems-fa9fa1e42233f5ee7da7d4a2b4ed0c5d848926f4.tar.bz2 | |
ColdFire ISA A+ instructions.
Diffstat (limited to 'cpukit/score/cpu/m68k/rtems/score')
| -rw-r--r-- | cpukit/score/cpu/m68k/rtems/score/cpu.h | 12 | ||||
| -rw-r--r-- | cpukit/score/cpu/m68k/rtems/score/m68k.h | 30 |
2 files changed, 34 insertions, 8 deletions
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h index 8f25254b4e..94dfdbfb02 100644 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h @@ -480,8 +480,18 @@ void _CPU_Thread_Idle_body( void ); #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); -#else +#elif ( M68K_HAS_ISA_APLUS == 1 ) + /* This is simplified by the fact that RTEMS never calls it with _value=0 */ +#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ + asm volatile ( \ + " swap %0\n" \ + " ff1.l %0\n" \ + : "=d" ((_output)) \ + : "0" ((_value)) \ + : "cc" ) ; + +#else /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in _CPU_Priority_bits_index is not needed), handles the 0 case, and does not molest _value -- jsg */ diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h index d4ef0b4451..49cee4510e 100644 --- a/cpukit/score/cpu/m68k/rtems/score/m68k.h +++ b/cpukit/score/cpu/m68k/rtems/score/m68k.h @@ -45,6 +45,7 @@ extern "C" { * -m68332 (no FP) (deprecated, use -mcpu32) * -mcpu32 (no FP) * -m5200 (no FP) + * -m528x (no FP, ISA A+) * * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between * the CPU32 and CPU32+. The option -mcpu32 generates code which can @@ -196,6 +197,20 @@ extern "C" { #define M68K_HAS_FPU 0 #define M68K_HAS_FPSP_PACKAGE 0 +#elif defined(__mcf528x__) +/* Motorola ColdFire ISA A+ - RISC/68020 hybrid */ +#define CPU_MODEL_NAME "m528x" +#define M68K_HAS_VBR 1 +#define M68K_HAS_BFFFO 0 +#define M68K_HAS_SEPARATE_STACKS 0 +#define M68K_HAS_PREINDEXING 0 +#define M68K_HAS_EXTB_L 1 +#define M68K_HAS_MISALIGNED 1 +#define M68K_HAS_FPU 0 +#define M68K_HAS_FPSP_PACKAGE 0 +#define M68K_COLDFIRE_ARCH 1 +#define M68K_HAS_ISA_APLUS 1 + #elif defined(__mcf5200__) /* Motorola ColdFire V2 core - RISC/68020 hybrid */ #define CPU_MODEL_NAME "m5200" @@ -208,6 +223,7 @@ extern "C" { #define M68K_HAS_FPU 0 #define M68K_HAS_FPSP_PACKAGE 0 #define M68K_COLDFIRE_ARCH 1 +#define M68K_HAS_ISA_APLUS 0 #elif defined(__mc68000__) @@ -316,14 +332,14 @@ extern "C" { asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) #elif ( M68K_COLDFIRE_ARCH == 1 ) -#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR +extern void *_ColdFire_VBR; +#define m68k_get_vbr( _vbr ) _vbr = _ColdFire_VBR -#define m68k_set_vbr( _vbr ) \ - asm volatile ("move.l %%a7,%%d1 \n\t" \ - "move.l %0,%%a7\n\t" \ - "movec %%a7,%%vbr\n\t" \ - "move.l %%d1,%%a7\n\t" \ - : : "d" (_vbr) : "d1" ); +#define m68k_set_vbr( vbr ) \ + do { \ + asm volatile ( "movec %0,%%vbr " : : "r" (vbr)); \ + _ColdFire_VBR = (void *)vbr; \ + } while(0) #else #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR |